Searched refs:CLKID_MPLL2 (Results 1 – 13 of 13) sorted by relevance
| /external/u-boot/drivers/clk/meson/ |
| D | axg.c | 43 MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
90 CLKID_MPLL2, in meson_clk81_get_rate()
167 case CLKID_MPLL2: in meson_mpll_get_rate()
261 case CLKID_MPLL2: in meson_clk_get_rate_by_id()
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| D | gxbb.c | 180 MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
577 CLKID_MPLL2, in meson_clk81_get_rate()
655 case CLKID_MPLL2: in meson_mpll_get_rate()
749 case CLKID_MPLL2: in meson_clk_get_rate_by_id()
824 case CLKID_MPLL2: in meson_clk_set_rate_by_id()
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| D | g12a.c | 572 CLKID_MPLL2, in meson_clk81_get_rate()
646 case CLKID_MPLL2: in meson_mpll_get_rate()
798 case CLKID_MPLL2: in meson_clk_get_rate_by_id()
905 case CLKID_MPLL2: in meson_clk_set_rate_by_id()
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| /external/u-boot/include/dt-bindings/clock/ |
| D | axg-clkc.h | 22 #define CLKID_MPLL2 13 macro
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| D | gxbb-clkc.h | 21 #define CLKID_MPLL2 15 macro
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| D | g12a-clkc.h | 22 #define CLKID_MPLL2 13 macro
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| /external/u-boot/arch/arm/dts/ |
| D | meson-g12b-khadas-vim3.dtsi | 58 assigned-clocks = <&clkc CLKID_MPLL2>,
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| D | meson-g12a-sei510.dts | 194 assigned-clocks = <&clkc CLKID_MPLL2>,
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| D | meson-g12b-odroid-n2.dts | 218 assigned-clocks = <&clkc CLKID_MPLL2>,
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| D | meson-axg.dtsi | 150 <&clkc CLKID_MPLL2>;
1002 <&clkc CLKID_MPLL2>,
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| D | meson-gxbb.dtsi | 288 <&clkc CLKID_MPLL2>;
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| D | meson-gxl.dtsi | 88 <&clkc CLKID_MPLL2>;
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| D | meson-g12-common.dtsi | 108 <&clkc CLKID_MPLL2>;
1490 <&clkc CLKID_MPLL2>,
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