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Searched refs:CLK_CPU (Results 1 – 16 of 16) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_axp_vars.h112 u32 cpu_fab_clk_to_hclk[FAB_OPT][CLK_CPU] =
139 u32 cpu_ddr_ratios[FAB_OPT][CLK_CPU] =
Dddr3_axp.h442 #define CLK_CPU 12 macro
443 #define CLK_VCO (2 * CLK_CPU)
Dddr3_dfs.c44 extern u8 div_ratio1to1[CLK_CPU][CLK_DDR];
45 extern u8 div_ratio2to1[CLK_CPU][CLK_DDR];
49 extern u32 cpu_fab_clk_to_hclk[FAB_OPT][CLK_CPU];
Dddr3_init.c762 ui_vco_freq = cpu_freq + CLK_CPU; in ddr3_get_vco_freq()
/external/u-boot/include/dt-bindings/clock/
Dmt7628-clk.h13 #define CLK_CPU 33 macro
Dsun8i-v3s-ccu.h49 #define CLK_CPU 14 macro
Dsun5i-ccu.h25 #define CLK_CPU 17 macro
Dsun6i-a31-ccu.h52 #define CLK_CPU 18 macro
Dsun8i-r40-ccu.h46 #define CLK_CPU 24 macro
Dsun4i-a10-ccu.h48 #define CLK_CPU 20 macro
/external/u-boot/drivers/clk/mtmips/
Dclk-mt7628.c42 [CLK_CPU] = CLK_SRC_CPU,
/external/u-boot/arch/arm/dts/
Dsun8i-v3s.dtsi61 clocks = <&ccu CLK_CPU>;
Dsun7i-a20.dtsi106 clocks = <&ccu CLK_CPU>;
125 clocks = <&ccu CLK_CPU>;
Dsun5i.dtsi62 clocks = <&ccu CLK_CPU>;
Dsun4i-a10.dtsi116 clocks = <&ccu CLK_CPU>;
Dsun6i-a31.dtsi106 clocks = <&ccu CLK_CPU>;