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Searched refs:CLK_DDR (Results 1 – 15 of 15) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_axp_vars.h167 u8 div_ratio1to1[CLK_VCO][CLK_DDR] =
196 u8 div_ratio2to1[CLK_VCO][CLK_DDR] =
Dddr3_dfs.c40 extern u8 div_ratio[CLK_VCO][CLK_DDR];
44 extern u8 div_ratio1to1[CLK_CPU][CLK_DDR];
45 extern u8 div_ratio2to1[CLK_CPU][CLK_DDR];
Dddr3_axp.h444 #define CLK_DDR 12 macro
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dclock.h29 CLK_DDR, enumerator
/external/u-boot/arch/arm/mach-rockchip/rk3288/
Drk3288.c163 { "dpll", CLK_DDR }, in do_clock()
/external/u-boot/drivers/clk/rockchip/
Dclk_rv1108.c50 case CLK_DDR: in rv1108_pll_id()
177 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); in rv1108_sfc_set_clk()
650 dpll = rkclk_pll_get_rate(cru, CLK_DDR); in rkclk_init()
Dclk_rk322x.c342 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg); in rk322x_ddr_set_clk()
386 case CLK_DDR: in rk322x_clk_set_rate()
Dclk_rk3188.c152 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); in rkclk_configure_ddr()
506 case CLK_DDR: in rk3188_clk_set_rate()
Dclk_rk3288.c208 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); in rkclk_configure_ddr()
800 case CLK_DDR: in rk3288_clk_set_rate()
Dclk_rk3368.c495 case CLK_DDR: in rk3368_clk_set_rate()
Dclk_rk3328.c219 case CLK_DDR: in rkclk_set_pll()
/external/u-boot/drivers/ram/rockchip/
Dsdram_rk322x.c801 priv->ddr_clk.id = CLK_DDR; in rk322x_dmc_probe()
Ddmc-rk3368.c943 priv->ddr_clk.id = CLK_DDR; in rk3368_dmc_probe()
Dsdram_rk3188.c906 priv->ddr_clk.id = CLK_DDR; in rk3188_dmc_probe()
Dsdram_rk3288.c1074 priv->ddr_clk.id = CLK_DDR; in rk3288_dmc_probe()