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Searched refs:CLK_USB_PHY0 (Results 1 – 25 of 27) sorted by relevance

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/external/u-boot/include/dt-bindings/clock/
Dsun8i-v3s-ccu.h88 #define CLK_USB_PHY0 56 macro
Dsun8i-a23-a33-ccu.h99 #define CLK_USB_PHY0 74 macro
Dsun5i-ccu.h81 #define CLK_USB_PHY0 77 macro
Dsun50i-a64-ccu.h106 #define CLK_USB_PHY0 86 macro
Dsun8i-a83t-ccu.h114 #define CLK_USB_PHY0 77 macro
Dsun8i-h3-ccu.h117 #define CLK_USB_PHY0 88 macro
Dsun50i-h6-ccu.h91 #define CLK_USB_PHY0 105 macro
Dsun6i-a31-ccu.h134 #define CLK_USB_PHY0 100 macro
Dsun8i-r40-ccu.h144 #define CLK_USB_PHY0 124 macro
/external/u-boot/drivers/clk/sunxi/
Dclk_v3s.c28 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
Dclk_a10s.c37 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
Dclk_a23.c34 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
Dclk_a83t.c36 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
Dclk_a64.c37 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
Dclk_h6.c32 [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
Dclk_a31.c44 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
Dclk_h3.c42 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
Dclk_r40.c48 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
/external/u-boot/arch/arm/dts/
Dsun8i-v3s.dtsi175 clocks = <&ccu CLK_USB_PHY0>;
Dsun50i-h6.dtsi439 clocks = <&ccu CLK_USB_PHY0>,
Dsun5i.dtsi332 clocks = <&ccu CLK_USB_PHY0>;
Dsun8i-a23-a33.dtsi226 clocks = <&ccu CLK_USB_PHY0>,
Dsun8i-r40.dtsi253 clocks = <&ccu CLK_USB_PHY0>,
Dsunxi-h3-h5.dtsi267 clocks = <&ccu CLK_USB_PHY0>,
Dsun50i-a64.dtsi431 clocks = <&ccu CLK_USB_PHY0>,

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