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Searched refs:COND1 (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Util/
Dlibcalls-shrinkwrap-double.ll11 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt double %value, -7.100000e+02
13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
21 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt double %value, -7.450000e+02
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
31 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt double %value, -1.074000e+03
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
41 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt double %value, -7.100000e+02
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
70 ; CHECK: [[COND1:%[0-9]+]] = fcmp ogt double %value, 1.000000e+00
72 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
[all …]
Dlibcalls-shrinkwrap-long-double.ll11 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00CB174000000000000
13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
21 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00CB21C000000000000
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
31 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00D807A000000000000
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
41 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt x86_fp80 %value, 0xKC00CB174000000000000
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
71 ; CHECK: [[COND1:%[0-9]+]] = fcmp ogt x86_fp80 %value, 0xK3FFF8000000000000000
73 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
[all …]
Dlibcalls-shrinkwrap-float.ll11 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt float %value, -8.900000e+01
13 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
21 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt float %value, -1.030000e+02
23 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
31 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt float %value, -1.490000e+02
33 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
41 ; CHECK: [[COND1:%[0-9]+]] = fcmp olt float %value, -8.900000e+01
43 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
71 ; CHECK: [[COND1:%[0-9]+]] = fcmp ogt float %value, 1.000000e+00
73 ; CHECK: [[COND:%[0-9]+]] = or i1 [[COND2]], [[COND1]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dabs_abs.ll696 ; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
697 ; CHECK-NEXT: ret i32 [[COND1]]
712 ; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
713 ; CHECK-NEXT: ret i32 [[COND1]]
728 ; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
729 ; CHECK-NEXT: ret i32 [[COND1]]
744 ; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
745 ; CHECK-NEXT: ret i32 [[COND1]]
760 ; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
761 ; CHECK-NEXT: ret i32 [[COND1]]
[all …]
Dcall_nonnull_arg.ll10 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i32* %a, null
11 ; CHECK-NEXT: br i1 [[COND1]], label %dead, label %not_null
Dselect_meta.ll109 ; CHECK-NEXT: [[COND1:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 %x, !prof ![[$MD3:[0-9]+]]
110 ; CHECK-NEXT: ret i32 [[COND1]]
127 ; CHECK-NEXT: [[COND1:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> %x, !prof ![…
128 ; CHECK-NEXT: ret <2 x i32> [[COND1]]
Dshift.ll431 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i8 [[TMP1]], 0
432 ; CHECK-NEXT: br i1 [[COND1]], label %bb2, label %bb1
/external/clang/test/CodeGenObjC/
Darc-loadweakretained-release.m53 // CHECK: [[COND1:%.*]] = phi i8**
54 // CHECK-NEXT: [[ICRISNULL:%.*]] = icmp eq i8** [[COND1]], null
65 // CHECK-NEXT: [[ICRISNULL1:%.*]] = icmp eq i8** [[COND1]], null
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IRCE/
Dstride_more_than_1.ll19 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp slt i32 0, %exit.mainloop.at
20 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preheader, label %main.pseudo.exit
84 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp slt i32 0, %exit.mainloop.at
85 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preheader, label %main.pseudo.exit
150 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp slt i32 0, %exit.mainloop.at
151 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preheader, label %main.pseudo.exit
258 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp sgt i32 100, %exit.preloop.at
259 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preloop.preheader, label %preloop.pseudo.exit
324 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 2147483640, %exit.preloop.at
325 ; CHECK-NEXT: br i1 [[COND1]], label %loop.preloop.preheader, label %preloop.pseudo.exit
[all …]
Dempty_ranges.ll31 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ult i32 %idx.next, 10
32 ; CHECK-NEXT: br i1 [[COND1]], label %loop, label %main.exit.selector
Dunsigned_comparisons_ugt.ll60 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 %len, 1
61 ; CHECK-NEXT: %umax = select i1 [[COND1]], i32 %len, i32 1
151 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 %len, 1
152 ; CHECK-NEXT: %umax = select i1 [[COND1]], i32 %len, i32 1
Dunsigned_comparisons_ult.ll63 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 %len, 1
64 ; CHECK-NEXT: %umax = select i1 [[COND1]], i32 %len, i32 1
196 ; CHECK-NEXT: [[COND1:%[^ ]+]] = icmp ugt i32 %len, 1
197 ; CHECK-NEXT: %umax = select i1 [[COND1]], i32 %len, i32 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopUnroll/
Dunroll-loop-invalidation.ll72 ; CHECK: %[[COND1:.*]] = icmp eq i32 %{{.*}}, %inner1.count
73 ; CHECK: br i1 %[[COND1]],
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/
DSpeculativeExec.ll45 ; CHECK-NEXT: [[COND1:%.*]] = load volatile i1, i1* [[DUMMY:%.*]]
46 ; CHECK-NEXT: br i1 [[COND1]], label [[IF:%.*]], label [[END:%.*]]
/external/llvm/test/Transforms/InstCombine/
Dshift.ll469 ; CHECK-NEXT: [[COND1:%.*]] = icmp slt i8 %x, 0
470 ; CHECK-NEXT: br i1 [[COND1]], label %bb1, label %bb2
492 ; CHECK-NEXT: [[COND1:%.*]] = icmp eq i8 [[TMP1]], 0
493 ; CHECK-NEXT: br i1 [[COND1]], label %bb2, label %bb1
/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_dec.h205 #define COND1 1 macro
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Duniform-cfg.ll251 ; GCN: s_load_dwordx2 s{{\[}}[[COND0:[0-9]+]]:[[COND1:[0-9]+]]{{\]}}
254 ; GCN: v_cmp_gt_i32_e64 {{[^,]*}}, s[[COND1]], 0{{$}}
/external/pcre/dist2/doc/
Dpcre2.txt9223 ( COND1 (*THEN) FOO | COND2 (*THEN) BAR | COND3 (*THEN) BAZ ) ...
9225 If the COND1 pattern matches, FOO is tried (and possibly further items
9228 into COND1. If that succeeds and BAR fails, COND3 is tried. If subse-