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Searched refs:CONFIG_HPS_CLK_F2S_SDR_REF_HZ (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/board/terasic/de1-soc/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
68 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/is1/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/altera/cyclone5-socdk/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/terasic/sockit/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/altera/arria5-socdk/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/devboards/dbm-soc1/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/softing/vining_fpga/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/terasic/de0-nano-soc/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/ebv/socrates/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/terasic/de10-nano/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/sr1500/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/board/aries/mcvevk/qts/
Dpll_config.h61 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 macro
/external/u-boot/arch/arm/mach-socfpga/
Dwrap_pll_config.c145 return CONFIG_HPS_CLK_F2S_SDR_REF_HZ; in cm_get_f2s_sdr_ref_clk_hz()
/external/u-boot/scripts/
Dconfig_whitelist.txt694 CONFIG_HPS_CLK_F2S_SDR_REF_HZ