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Searched refs:CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/board/is1/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/altera/cyclone5-socdk/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/terasic/sockit/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/altera/arria5-socdk/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/devboards/dbm-soc1/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/softing/vining_fpga/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/terasic/de0-nano-soc/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/ebv/socrates/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/terasic/de10-nano/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/sr1500/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/aries/mcvevk/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/board/terasic/de1-soc/qts/
Dpll_config.h53 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 macro
/external/u-boot/arch/arm/mach-socfpga/
Dwrap_pll_config.c106 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
/external/u-boot/scripts/
Dconfig_whitelist.txt748 CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE