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Searched refs:CPG_PLL0CR (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/clk/renesas/
Dclk-rcar-gen2.c26 #define CPG_PLL0CR 0x00d8 macro
153 value = readl(priv->base + CPG_PLL0CR); in gen2_clk_get_rate()
Dclk-rcar-gen3.c27 #define CPG_PLL0CR 0x00d8 macro
212 value = readl(priv->base + CPG_PLL0CR); in gen3_clk_get_rate64()
/external/arm-trusted-firmware/plat/renesas/rcar/include/
Drcar_def.h221 #define CPG_PLL0CR (CPG_BASE + 0x00D8U) macro
/external/arm-trusted-firmware/plat/renesas/rcar/
Dbl2_plat_setup.c952 reg = mmio_read_32(CPG_PLL0CR); in bl2_el3_early_platform_setup()
954 mmio_write_32(CPG_PLL0CR, reg); in bl2_el3_early_platform_setup()