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Searched refs:CPG_PLL4CR (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/drivers/clk/renesas/
Dclk-rcar-gen3.c29 #define CPG_PLL4CR 0x01f4 macro
246 value = readl(priv->base + CPG_PLL4CR); in gen3_clk_get_rate64()
/external/arm-trusted-firmware/plat/renesas/rcar/include/
Drcar_def.h223 #define CPG_PLL4CR (CPG_BASE + 0x01F4U) macro
/external/arm-trusted-firmware/plat/renesas/rcar/
Dbl2_plat_setup.c948 reg = mmio_read_32(CPG_PLL4CR); in bl2_el3_early_platform_setup()
950 mmio_write_32(CPG_PLL4CR, reg); in bl2_el3_early_platform_setup()