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/external/llvm/test/CodeGen/PowerPC/
Dopt-cmp-inst-cr0-live.ll8 ; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>;
12 ; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>;
13 ; CHECK: COPY %CR0
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmWriter.inc6818 MI->getOperand(1).getReg() == PPC::CR0) {
6819 // (BCC 12, CR0, condbrtarget:$dst)
6835 MI->getOperand(1).getReg() == PPC::CR0) {
6836 // (BCC 14, CR0, condbrtarget:$dst)
6852 MI->getOperand(1).getReg() == PPC::CR0) {
6853 // (BCC 15, CR0, condbrtarget:$dst)
6869 MI->getOperand(1).getReg() == PPC::CR0) {
6870 // (BCC 44, CR0, condbrtarget:$dst)
6886 MI->getOperand(1).getReg() == PPC::CR0) {
6887 // (BCC 46, CR0, condbrtarget:$dst)
[all …]
/external/capstone/arch/PowerPC/
DPPCGenAsmWriter.inc4309 // (BCC 12, CR0, condbrtarget:$dst)
4326 // (BCC 14, CR0, condbrtarget:$dst)
4343 // (BCC 15, CR0, condbrtarget:$dst)
4360 // (BCC 44, CR0, condbrtarget:$dst)
4377 // (BCC 46, CR0, condbrtarget:$dst)
4394 // (BCC 47, CR0, condbrtarget:$dst)
4411 // (BCC 76, CR0, condbrtarget:$dst)
4428 // (BCC 78, CR0, condbrtarget:$dst)
4445 // (BCC 79, CR0, condbrtarget:$dst)
4462 // (BCC 68, CR0, condbrtarget:$dst)
[all …]
/external/clang/lib/Headers/
Dhtmintrin.h40 #define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3) argument
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrHTM.td89 // All HTM instructions, with the exception of tcheck, set CR0 with the
91 // instruction is executed. For tbegin., the EQ bit in CR0 can be used
DPPCRegisterInfo.h30 Reg = PPC::CR0; in getCRFromCRBit()
DPPCInstrInfo.td922 let Defs = [CR0] in
937 let Defs = [CARRY, CR0] in
952 let Defs = [CARRY, CR0] in
966 let Defs = [CR0] in
980 let Defs = [CR0] in
996 let Defs = [CR0] in
1012 let Defs = [CARRY, CR0] in
1026 let Defs = [CR0] in
1041 let Defs = [CARRY, CR0] in
1055 let Defs = [CR0] in
[all …]
DPPCRegisterInfo.td202 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
369 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
372 def CRRC0 : RegisterClass<"PPC", [i32], 32, (add CR0)>;
DPPCInstr64Bit.td203 let Defs = [CR0] in {
261 let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
468 let Defs = [CR0] in {
790 let Defs = [CR0] in
799 let Defs = [CR0] in
1117 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1126 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1149 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1158 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
/external/llvm/lib/Target/PowerPC/
DPPCInstrHTM.td89 // All HTM instructions, with the exception of tcheck, set CR0 with the
91 // instruction is executed. For tbegin., the EQ bit in CR0 can be used
DPPCInstrInfo.td807 let Defs = [CR0] in
822 let Defs = [CARRY, CR0] in
837 let Defs = [CARRY, CR0] in
851 let Defs = [CR0] in
865 let Defs = [CR0] in
881 let Defs = [CR0] in
897 let Defs = [CARRY, CR0] in
911 let Defs = [CR0] in
926 let Defs = [CARRY, CR0] in
940 let Defs = [CR0] in
[all …]
DPPCRegisterInfo.h30 Reg = PPC::CR0; in getCRFromCRBit()
DPPCRegisterInfo.td194 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
344 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
347 def CRRC0 : RegisterClass<"PPC", [i32], 32, (add CR0)>;
DPPCInstr64Bit.td208 let Defs = [CR0] in {
254 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
461 let Defs = [CR0] in {
675 let Defs = [CR0] in
684 let Defs = [CR0] in
979 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
988 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
1011 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
1020 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
DPPCInstrInfo.cpp1658 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) || in optimizeCompareInstr()
1659 Instr.readsRegister(PPC::CR0, TRI))) in optimizeCompareInstr()
1764 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); in optimizeCompareInstr()
1768 MI->clearRegisterDeads(PPC::CR0); in optimizeCompareInstr()
1794 assert(MI->definesRegister(PPC::CR0) && in optimizeCompareInstr()
/external/kernel-headers/original/uapi/asm-generic/
Dtermbits.h92 #define CR0 0000000 macro
/external/llvm/lib/Transforms/Scalar/
DGuardWidening.cpp416 ConstantRange CR0 = in widenCondCommon() local
430 auto SubsetIntersect = CR0.inverse().unionWith(CR1.inverse()).inverse(); in widenCondCommon()
431 auto SupersetIntersect = CR0.intersectWith(CR1); in widenCondCommon()
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 …ters: CS DS EFLAGS EIP EIZ ES FPSW FS GS IP RIP RIZ SS BND0 BND1 BND2 BND3 CR0 CR1 CR2 CR3 CR4 CR5…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/
DGuardWidening.cpp473 ConstantRange CR0 = in widenCondCommon() local
487 auto SubsetIntersect = CR0.inverse().unionWith(CR1.inverse()).inverse(); in widenCondCommon()
488 auto SupersetIntersect = CR0.intersectWith(CR1); in widenCondCommon()
/external/python/cpython2/Modules/
Dtermios.c447 #ifdef CR0
448 {"CR0", CR0},
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp349 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); in get_crbitm_encoding()
363 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); in getMachineOpValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp353 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); in get_crbitm_encoding()
366 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); in getMachineOpValue()
/external/python/cpython3/Modules/
Dtermios.c475 #ifdef CR0
476 {"CR0", CR0},
/external/python/cpython2/Lib/plat-irix5/
DIOCTL.py107 CR0 = 0 variable
/external/python/cpython2/Lib/plat-irix6/
DIOCTL.py107 CR0 = 0 variable

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