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Searched refs:CRF_APB_DDR_CTRL (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/drivers/clk/
Dclk_zynqmp.c33 #define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60) macro
195 return CRF_APB_DDR_CTRL; in zynqmp_clk_get_register()
399 ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl); in zynqmp_clk_get_ddr_rate()
/external/arm-trusted-firmware/plat/xilinx/zynqmp/include/
Dzynqmp_def.h273 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) macro
/external/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/
Dpm_api_clock.c1316 .control_reg = CRF_APB_DDR_CTRL,