1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ZYNQMP_DEF_H 8 #define ZYNQMP_DEF_H 9 10 #include <plat/common/common_def.h> 11 12 #define ZYNQMP_CONSOLE_ID_cadence 1 13 #define ZYNQMP_CONSOLE_ID_cadence0 1 14 #define ZYNQMP_CONSOLE_ID_cadence1 2 15 #define ZYNQMP_CONSOLE_ID_dcc 3 16 17 #define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) 18 19 /* Firmware Image Package */ 20 #define ZYNQMP_PRIMARY_CPU 0 21 22 /* Memory location options for Shared data and TSP in ZYNQMP */ 23 #define ZYNQMP_IN_TRUSTED_SRAM 0 24 #define ZYNQMP_IN_TRUSTED_DRAM 1 25 26 /******************************************************************************* 27 * ZYNQMP memory map related constants 28 ******************************************************************************/ 29 /* Aggregate of all devices in the first GB */ 30 #define DEVICE0_BASE U(0xFF000000) 31 #define DEVICE0_SIZE U(0x00E00000) 32 #define DEVICE1_BASE U(0xF9000000) 33 #define DEVICE1_SIZE U(0x00800000) 34 35 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 36 #define CRF_APB_BASE U(0xFD1A0000) 37 #define CRF_APB_SIZE U(0x00600000) 38 #define CRF_APB_CLK_BASE U(0xFD1A0020) 39 40 /* CRF registers and bitfields */ 41 #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) 42 43 #define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) 44 #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) 45 46 /* CRL registers and bitfields */ 47 #define CRL_APB_BASE U(0xFF5E0000) 48 #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) 49 #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) 50 #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) 51 #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) 52 #define CRL_APB_CLK_BASE U(0xFF5E0020) 53 54 #define CRL_APB_RPU_AMBA_RESET (U(1) << 2) 55 #define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) 56 57 #define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) 58 59 #define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) 60 #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) 61 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) 62 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) 63 #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ 64 CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) 65 #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \ 66 CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) 67 #define ZYNQMP_BOOTMODE_JTAG U(0) 68 #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ 69 CRL_APB_BOOT_DRIVE_PIN_1) 70 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 71 72 /* system counter registers and bitfields */ 73 #define IOU_SCNTRS_BASE 0xFF260000 74 #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) 75 76 /* APU registers and bitfields */ 77 #define APU_BASE 0xFD5C0000 78 #define APU_CONFIG_0 (APU_BASE + 0x20) 79 #define APU_RVBAR_L_0 (APU_BASE + 0x40) 80 #define APU_RVBAR_H_0 (APU_BASE + 0x44) 81 #define APU_PWRCTL (APU_BASE + 0x90) 82 83 #define APU_CONFIG_0_VINITHI_SHIFT 8 84 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 85 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 86 #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 87 #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 88 89 /* PMU registers and bitfields */ 90 #define PMU_GLOBAL_BASE 0xFFD80000 91 #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) 92 #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) 93 #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) 94 #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) 95 #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) 96 #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) 97 98 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) 99 100 /******************************************************************************* 101 * CCI-400 related constants 102 ******************************************************************************/ 103 #define PLAT_ARM_CCI_BASE 0xFD6E0000 104 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 105 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 106 107 /******************************************************************************* 108 * GIC-400 & interrupt handling related constants 109 ******************************************************************************/ 110 #define BASE_GICD_BASE 0xF9010000 111 #define BASE_GICC_BASE 0xF9020000 112 #define BASE_GICH_BASE 0xF9040000 113 #define BASE_GICV_BASE 0xF9060000 114 115 #if ZYNQMP_WDT_RESTART 116 #define IRQ_SEC_IPI_APU 67 117 #define IRQ_TTC3_1 77 118 #define TTC3_BASE_ADDR 0xFF140000 119 #define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) 120 #define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) 121 #endif 122 123 #define ARM_IRQ_SEC_PHY_TIMER 29 124 125 #define ARM_IRQ_SEC_SGI_0 8 126 #define ARM_IRQ_SEC_SGI_1 9 127 #define ARM_IRQ_SEC_SGI_2 10 128 #define ARM_IRQ_SEC_SGI_3 11 129 #define ARM_IRQ_SEC_SGI_4 12 130 #define ARM_IRQ_SEC_SGI_5 13 131 #define ARM_IRQ_SEC_SGI_6 14 132 #define ARM_IRQ_SEC_SGI_7 15 133 134 #define MAX_INTR_EL3 128 135 136 /******************************************************************************* 137 * UART related constants 138 ******************************************************************************/ 139 #define ZYNQMP_UART0_BASE 0xFF000000 140 #define ZYNQMP_UART1_BASE 0xFF010000 141 142 #if ZYNQMP_CONSOLE_IS(cadence) || ZYNQMP_CONSOLE_IS(dcc) 143 # define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE 144 #elif ZYNQMP_CONSOLE_IS(cadence1) 145 # define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE 146 #else 147 # error "invalid ZYNQMP_CONSOLE" 148 #endif 149 150 #define ZYNQMP_CRASH_UART_BASE ZYNQMP_UART_BASE 151 /* impossible to call C routine how it is done now - hardcode any value */ 152 #define ZYNQMP_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */ 153 /* Must be non zero */ 154 #define ZYNQMP_UART_BAUDRATE 115200 155 156 /* Silicon version detection */ 157 #define ZYNQMP_SILICON_VER_MASK 0xF000 158 #define ZYNQMP_SILICON_VER_SHIFT 12 159 #define ZYNQMP_CSU_VERSION_SILICON 0 160 #define ZYNQMP_CSU_VERSION_QEMU 3 161 162 #define ZYNQMP_RTL_VER_MASK 0xFF0 163 #define ZYNQMP_RTL_VER_SHIFT 4 164 165 #define ZYNQMP_PS_VER_MASK 0xF 166 #define ZYNQMP_PS_VER_SHIFT 0 167 168 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 169 #define ZYNQMP_CSU_IDCODE_OFFSET 0x40 170 171 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0 172 #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFF << \ 173 ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) 174 #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 175 176 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 177 #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << \ 178 ZYNQMP_CSU_IDCODE_SVD_SHIFT) 179 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 180 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xF << \ 181 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 182 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19 183 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3 << \ 184 ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) 185 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21 186 #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7F << \ 187 ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) 188 #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 189 190 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28 191 #define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xF << \ 192 ZYNQMP_CSU_IDCODE_REVISION_SHIFT) 193 #define ZYNQMP_CSU_IDCODE_REVISION 0 194 195 #define ZYNQMP_CSU_VERSION_OFFSET 0x44 196 197 /* Efuse */ 198 #define EFUSE_BASEADDR 0xFFCC0000 199 #define EFUSE_IPDISABLE_OFFSET 0x1018 200 #define EFUSE_IPDISABLE_VERSION 0x1FFU 201 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 202 203 /* Access control register defines */ 204 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 205 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 206 207 #define FPD_SLCR_BASEADDR U(0xFD610000) 208 #define IOU_SLCR_BASEADDR U(0xFF180000) 209 210 #define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) 211 #define ZYNQMP_RPU0_CFG U(0xFF9A0100) 212 #define ZYNQMP_RPU1_CFG U(0xFF9A0200) 213 #define ZYNQMP_SLSPLIT_MASK U(0x08) 214 #define ZYNQMP_TCM_COMB_MASK U(0x40) 215 #define ZYNQMP_SLCLAMP_MASK U(0x10) 216 #define ZYNQMP_VINITHI_MASK U(0x04) 217 218 /* Tap delay bypass */ 219 #define IOU_TAPDLY_BYPASS U(0XFF180390) 220 #define TAP_DELAY_MASK U(0x7) 221 222 /* SGMII mode */ 223 #define IOU_GEM_CTRL U(0xFF180360) 224 #define IOU_GEM_CLK_CTRL U(0xFF180308) 225 #define SGMII_SD_MASK U(0x3) 226 #define SGMII_SD_OFFSET U(2) 227 #define SGMII_PCS_SD_0 U(0x0) 228 #define SGMII_PCS_SD_1 U(0x1) 229 #define SGMII_PCS_SD_PHY U(0x2) 230 #define GEM_SGMII_MASK U(0x4) 231 #define GEM_CLK_CTRL_MASK U(0xF) 232 #define GEM_CLK_CTRL_OFFSET U(5) 233 #define GEM_RX_SRC_SEL_GTR U(0x1) 234 #define GEM_SGMII_MODE U(0x4) 235 236 /* SD DLL reset */ 237 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 238 #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) 239 #define ZYNQMP_SD0_DLL_RST U(0x00000004) 240 #define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) 241 #define ZYNQMP_SD1_DLL_RST U(0x00040000) 242 243 /* SD tap delay */ 244 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 245 #define ZYNQMP_SD_ITAP_DLY U(0xFF180314) 246 #define ZYNQMP_SD_OTAP_DLY U(0xFF180318) 247 #define ZYNQMP_SD_TAP_OFFSET U(16) 248 #define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) 249 #define ZYNQMP_SD_ITAPCHGWIN U(0x200) 250 #define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) 251 #define ZYNQMP_SD_ITAPDLYENA U(0x100) 252 #define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) 253 #define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) 254 #define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) 255 #define ZYNQMP_SD_OTAPDLYENA U(0x40) 256 257 /* Clock control registers */ 258 /* Full power domain clocks */ 259 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) 260 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) 261 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) 262 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) 263 #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) 264 #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) 265 #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) 266 /* Peripheral clocks */ 267 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) 268 #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) 269 #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) 270 #define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) 271 #define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) 272 #define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) 273 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) 274 #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) 275 #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) 276 #define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) 277 #define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) 278 #define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) 279 #define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) 280 #define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) 281 #define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) 282 #define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) 283 284 /* Low power domain clocks */ 285 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) 286 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) 287 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) 288 #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) 289 #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) 290 /* Peripheral clocks */ 291 #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) 292 #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) 293 #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) 294 #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) 295 #define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) 296 #define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) 297 #define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) 298 #define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) 299 #define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) 300 #define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) 301 #define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) 302 #define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) 303 #define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) 304 #define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) 305 #define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) 306 #define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) 307 #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) 308 #define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) 309 #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) 310 #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) 311 #define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) 312 #define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) 313 #define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) 314 #define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) 315 #define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) 316 #define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) 317 #define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) 318 #define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) 319 #define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) 320 #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) 321 #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) 322 #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) 323 #define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) 324 #define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) 325 #define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) 326 #define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) 327 #define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) 328 #define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) 329 #define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) 330 #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) 331 #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) 332 #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) 333 #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) 334 335 /* Global general storage register base address */ 336 #define GGS_BASEADDR (0xFFD80030U) 337 #define GGS_NUM_REGS U(4) 338 339 /* Persistent global general storage register base address */ 340 #define PGGS_BASEADDR (0xFFD80050U) 341 #define PGGS_NUM_REGS U(4) 342 343 /* Warm restart boot health status register and mask */ 344 #define PM_BOOT_HEALTH_STATUS_REG (GGS_BASEADDR + U(0x10)) 345 #define PM_BOOT_HEALTH_STATUS_MASK U(0x01) 346 347 /*AFI registers */ 348 #define AFIFM6_WRCTRL U(13) 349 #define FABRIC_WIDTH U(3) 350 351 #endif /* ZYNQMP_DEF_H */ 352