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Searched refs:CRL_APB_PLL_STATUS (Results 1 – 3 of 3) sorted by relevance

/external/arm-trusted-firmware/plat/xilinx/zynqmp/include/
Dzynqmp_def.h287 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) macro
/external/u-boot/drivers/clk/
Dclk_zynqmp.c47 #define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20) macro
/external/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/
Dpm_api_clock.c1181 .status_reg = CRL_APB_PLL_STATUS,