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Searched refs:CRU_PLL_CON (Results 1 – 7 of 7) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/
Dsoc.c59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
68 CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); in set_pll_normal_mode()
78 CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); in set_pll_bypass()
126 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
128 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in restore_pll()
129 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in restore_pll()
130 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in restore_pll()
131 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in restore_pll()
132 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in restore_pll()
135 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in restore_pll()
[all …]
Dsoc.h16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) macro
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Dsuspend.c648 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in pmusram_restore_pll()
650 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in pmusram_restore_pll()
651 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in pmusram_restore_pll()
652 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in pmusram_restore_pll()
653 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in pmusram_restore_pll()
654 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in pmusram_restore_pll()
656 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in pmusram_restore_pll()
658 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & in pmusram_restore_pll()
703 dpll_data[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, i)); in dmc_suspend()
Ddfs.c1716 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; in ddr_get_rate()
1717 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; in ddr_get_rate()
1719 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; in ddr_get_rate()
1721 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; in ddr_get_rate()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dpmu.c586 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
599 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
619 pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> in clst_pwr_domain_resume()
1297 (i >= CRU_PLL_CON(ABPLL_ID, 0) && in cru_register_restore()
1298 i <= CRU_PLL_CON(DPLL_ID, 5))) in cru_register_restore()
1301 if ((i == CRU_PLL_CON(ALPLL_ID, 2)) || in cru_register_restore()
1302 (i == CRU_PLL_CON(CPLL_ID, 2)) || in cru_register_restore()
1303 (i == CRU_PLL_CON(GPLL_ID, 2)) || in cru_register_restore()
1304 (i == CRU_PLL_CON(NPLL_ID, 2)) || in cru_register_restore()
1305 (i == CRU_PLL_CON(VPLL_ID, 2))) in cru_register_restore()
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dsdram_px30.h71 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) macro
Dsdram_rk3328.h51 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) macro