| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | cond-sel-value-prop.ll | 50 ; CSINC to materialize the 1.
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| D | arm64-early-ifcvt.ll | 396 ; This function from 175.vpr folds an ADDWri into a CSINC.
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 47 CSINC, // Conditional select increment. enumerator
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| D | AArch64SchedCyclone.td | 145 // CSEL,CSINC,CSINV,CSNEG
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| D | AArch64SchedKryoDetails.td | 550 (instregex "(CSINC|CSNEG)(W|X)r")>;
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| D | AArch64ISelLowering.cpp | 846 case AArch64ISD::CSINC: return "AArch64ISD::CSINC"; in getTargetNodeName()
4005 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC()
4013 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC()
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| D | AArch64InstrInfo.td | 175 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
1115 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 85 #define CSINC 0x9a800400 macro
1753 FAIL_IF(push_inst(compiler, CSINC | (cc << 12) | RD(dst_r) | RN(TMP_ZERO) | RM(TMP_ZERO))); in sljit_emit_op_flags()
1778 FAIL_IF(push_inst(compiler, CSINC | (cc << 12) | RD(TMP_REG2) | RN(TMP_ZERO) | RM(TMP_ZERO))); in sljit_emit_op_flags()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 47 CSINC, // Conditional select increment. enumerator
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| D | AArch64SchedThunderX2T99.td | 433 "CSINC(W|X)r", "CSINV(W|X)r",
455 "CSINC(W|X)r", "CSINV(W|X)r",
474 "CSINC(W|X)r", "CSINV(W|X)r",
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| D | AArch64SchedCyclone.td | 147 // CSEL,CSINC,CSINV,CSNEG
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| D | AArch64SchedFalkorDetails.td | 895 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
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| D | AArch64SchedKryoDetails.td | 550 (instregex "(CSINC|CSNEG)(W|X)r")>;
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| D | AArch64ISelLowering.cpp | 1097 case AArch64ISD::CSINC: return "AArch64ISD::CSINC"; in getTargetNodeName()
4649 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC()
4657 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC()
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| D | AArch64InstrInfo.td | 206 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
1311 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-early-ifcvt.ll | 396 ; This function from 175.vpr folds an ADDWri into a CSINC.
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| /external/v8/src/codegen/arm64/ |
| D | constants-arm64.h | 1030 CSINC = CSINC_w, enumerator
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| D | assembler-arm64.cc | 1006 ConditionalSelect(rd, rn, rm, cond, CSINC); in csinc()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1261 CSINC = CSINC_w, enumerator
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| D | assembler-aarch64.cc | 736 ConditionalSelect(rd, rn, rm, cond, CSINC); in csinc()
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 746 ### CSINC ### subsection
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenDAGISel.inc | 30451 /* 58283*/ /*SwitchOpcode*/ 45, TARGET_VAL(AArch64ISD::CSINC),// ->58331
|