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Searched refs:CTX_GPREGS_OFFSET (Results 1 – 11 of 11) sorted by relevance

/external/arm-trusted-firmware/lib/cpus/aarch64/
Dwa_cve_2017_5715_bpiall.S26 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
27 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
28 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
29 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
30 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
31 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
32 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
33 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
34 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
35 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
[all …]
Dwa_cve_2017_5715_mmu.S20 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
60 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
Dneoverse_n1.S549 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
550 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
551 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
552 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Ddenver.S34 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
49 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
Dcortex_a76.S41 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
106 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
/external/arm-trusted-firmware/lib/el3_runtime/aarch64/
Dcontext.S329 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
330 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
331 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
332 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
333 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
334 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
335 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
336 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
337 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
338 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
[all …]
/external/arm-trusted-firmware/bl31/aarch64/
Dea_delegate.S52 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
65 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
66 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
67 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
111 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
112 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
113 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
117 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
134 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Druntime_exceptions.S62 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
84 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
101 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
104 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
118 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
453 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
457 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
/external/arm-trusted-firmware/include/lib/el3_runtime/aarch64/
Dcontext.h16 #define CTX_GPREGS_OFFSET U(0x0) macro
56 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
334 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
/external/arm-trusted-firmware/docs/security_advisories/
Dsecurity-advisory-tfv-8.rst49 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
50 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
/external/arm-trusted-firmware/bl1/aarch64/
Dbl1_exceptions.S85 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]