Home
last modified time | relevance | path

Searched refs:CTX_SPSR_EL3 (Results 1 – 11 of 11) sorted by relevance

/external/arm-trusted-firmware/bl31/aarch64/
Dea_delegate.S245 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
295 ldp x1, x2, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Druntime_exceptions.S145 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
403 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
/external/arm-trusted-firmware/services/spd/trusty/
Dtrusty.c152 ctx->fiq_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3); in trusty_fiq_handler()
173 ctx->fiq_handler_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3); in trusty_set_fiq_handler()
293 CTX_SPSR_EL3)); in trusty_init()
/external/arm-trusted-firmware/lib/el3_runtime/aarch64/
Dcontext_mgmt.c258 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); in cm_setup_context()
607 write_ctx_reg(state, CTX_SPSR_EL3, spsr); in cm_set_elr_spsr_el3()
Dcontext.S503 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
/external/arm-trusted-firmware/plat/nvidia/tegra/common/
Dtegra_fiq_glue.c79 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); in tegra_fiq_interrupt_handler()
/external/arm-trusted-firmware/services/spd/tspd/
Dtspd_main.c130 CTX_SPSR_EL3); in tspd_sel1_interrupt_handler()
329 CTX_SPSR_EL3, in tspd_smc_handler()
/external/arm-trusted-firmware/plat/arm/common/aarch64/
Dexecution_state_switch.c62 spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3); in arm_execution_state_switch()
/external/arm-trusted-firmware/services/std_svc/sdei/
Dsdei_intr_mgmt.c172 disp_ctx->spsr_el3 = read_ctx_reg(tgt_el3, CTX_SPSR_EL3); in save_event_ctx()
192 write_ctx_reg(tgt_el3, CTX_SPSR_EL3, disp_ctx->spsr_el3); in restore_event_ctx()
/external/arm-trusted-firmware/bl1/aarch64/
Dbl1_exceptions.S273 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
/external/arm-trusted-firmware/include/lib/el3_runtime/aarch64/
Dcontext.h60 #define CTX_SPSR_EL3 U(0x18) macro