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Searched refs:CpuFeature (Results 1 – 10 of 10) sorted by relevance

/external/v8/src/codegen/
Dassembler.h234 bool IsEnabled(CpuFeature f) { in IsEnabled()
237 void EnableCpuFeature(CpuFeature f) { in EnableCpuFeature()
413 CpuFeatureScope(AssemblerBase* assembler, CpuFeature f,
421 CpuFeatureScope(AssemblerBase* assembler, CpuFeature f,
Dcpu-features.h15 enum CpuFeature { enum
98 static bool IsSupported(CpuFeature f) { in IsSupported()
Dassembler.cc170 CpuFeatureScope::CpuFeatureScope(AssemblerBase* assembler, CpuFeature f, in CpuFeatureScope()
/external/v8/src/compiler/backend/
Dinstruction-selector.h366 explicit Features(CpuFeature f) : bits_(1u << f) {} in Features()
367 Features(CpuFeature f1, CpuFeature f2) : bits_((1u << f1) | (1u << f2)) {} in Features()
369 bool Contains(CpuFeature f) const { return (bits_ & (1u << f)); } in Contains()
375 bool IsSupported(CpuFeature feature) const { in IsSupported()
/external/v8/src/codegen/x64/
Dmacro-assembler-x64.h67 base::Optional<CpuFeature> feature = base::nullopt;
112 AvxHelper<Dst, Args...>{this, base::Optional<CpuFeature>(SSE3)} \
119 AvxHelper<Dst, Args...>{this, base::Optional<CpuFeature>(SSSE3)} \
126 AvxHelper<Dst, Args...>{this, base::Optional<CpuFeature>(SSE4_1)} \
132 AvxHelper<Dst, Args...>{this, base::Optional<CpuFeature>(SSE4_2)} \
Dmacro-assembler-x64.cc1771 base::Optional<CpuFeature> feature = base::nullopt) { in PinsrHelper()
1794 imm8, base::Optional<CpuFeature>(SSE4_1)); in Pinsrb()
1800 imm8, base::Optional<CpuFeature>(SSE4_1)); in Pinsrb()
1821 imm8, base::Optional<CpuFeature>(SSE4_1)); in Pinsrd()
1840 imm8, base::Optional<CpuFeature>(SSE4_1)); in Pinsrd()
1864 imm8, base::Optional<CpuFeature>(SSE4_1)); in Pinsrq()
1870 imm8, base::Optional<CpuFeature>(SSE4_1)); in Pinsrq()
/external/cpu_features/
DCMakeLists.txt145 add_executable(CpuFeature::list_cpu_features ALIAS list_cpu_features)
/external/v8/src/wasm/baseline/x64/
Dliftoff-assembler-x64.h2116 LiftoffRegister rhs, base::Optional<CpuFeature> feature = base::nullopt) {
2138 LiftoffRegister rhs, base::Optional<CpuFeature> feature = base::nullopt) {
2911 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i8x16_min_s()
2925 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i8x16_max_s()
3060 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i16x8_min_u()
3074 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i16x8_max_u()
3156 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i32x4_mul()
3163 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i32x4_min_s()
3170 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i32x4_min_u()
3177 this, dst, lhs, rhs, base::Optional<CpuFeature>(SSE4_1)); in emit_i32x4_max_s()
[all …]
/external/v8/src/codegen/mips/
Dconstants-mips.h102 return CpuFeatures::IsSupported(static_cast<CpuFeature>(check)); in IsMipsArchVariant()
/external/v8/src/wasm/baseline/ia32/
Dliftoff-assembler-ia32.h2491 LiftoffRegister rhs, base::Optional<CpuFeature> feature = base::nullopt) {
2513 LiftoffRegister rhs, base::Optional<CpuFeature> feature = base::nullopt) {