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Searched refs:DDR_CTRL_UPD_EMRS (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/mips/mach-ath79/ar933x/
Dddr.c18 #define DDR_CTRL_UPD_EMRS BIT(1) macro
140 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
164 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
169 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
204 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
/external/u-boot/arch/mips/mach-ath79/qca953x/
Dddr.c18 #define DDR_CTRL_UPD_EMRS BIT(1) macro
262 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
352 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
386 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
394 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()