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Searched refs:DRAM_SEL_CFG (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/arch/arm/mach-imx/imx8m/
Dclock_imx8mm.c165 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_enable_bypass()
171 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_disable_bypass()
Dclock_imx8mq.c566 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_enable_bypass()
572 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | in dram_disable_bypass()
Dclock_slice.c471 {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
537 {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
/external/u-boot/arch/arm/include/asm/arch-imx8m/
Dclock_imx8mm.h73 DRAM_SEL_CFG = 48, enumerator
154 DRAM_SEL_CFG = 48, enumerator
Dclock_imx8mq.h46 DRAM_SEL_CFG = 48, enumerator