| /external/u-boot/arch/arm/include/asm/ |
| D | barriers.h | 34 #define DSB asm volatile ("dsb sy" : : : "memory") macro
38 #define DSB CP15DSB macro
42 #define DSB CP15DSB macro
47 #define dsb() DSB
|
| /external/libavc/common/arm/ |
| D | ih264_arm_memory_barrier.s | 45 @* Description : Adds DSB
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | invalid-barrier.s | 14 @ DSB
|
| D | basic-arm-instructions-v8.s | 37 @ DSB (v8 barriers)
|
| D | basic-thumb2-instructions-v8.s | 77 @ DSB (ARMv8-only barriers)
|
| /external/llvm/test/MC/ARM/ |
| D | invalid-barrier.s | 14 @ DSB
|
| D | basic-arm-instructions-v8.s | 37 @ DSB (v8 barriers)
|
| D | basic-thumb2-instructions-v8.s | 67 @ DSB (ARMv8-only barriers)
|
| /external/u-boot/arch/arm/mach-imx/ |
| D | cache.c | 36 DSB; in enable_ca7_smp()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | intrinsics-memory-barrier.ll | 31 ; Similarly for DSB.
|
| /external/llvm/test/CodeGen/ARM/ |
| D | intrinsics-memory-barrier.ll | 27 ; Similarly for DSB.
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | intrinsics-memory-barrier.ll | 31 ; Similarly for DSB.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | intrinsics-memory-barrier.ll | 27 ; Similarly for DSB.
|
| /external/u-boot/arch/arm/cpu/armv7/ |
| D | start.S | 102 mcr p15, 0, r0, c7, c10, 4 @ DSB
147 mcr p15, 0, r0, c7, c10, 4 @ DSB
|
| /external/u-boot/arch/arm/mach-omap2/omap3/ |
| D | lowlevel_init.S | 33 mcr p15, 0, r0, c7, c10, 4 @ DSB
|
| /external/walt/hardware/enclosure/ |
| D | WALT_recessed_enclosure.stl | 28 …@���@DSB�>�@��L@��� �6�J�����DSB�>�@��L@��SB�t�@���@DSB�>�@���@���P���P�����DSB�>�@��L@DSB�…
93 …|B���@DSBűB��L@���P���P?����DSBűB��L@��RB�|B���@DSBűB���@��� �6�J?����DSBűB��L@DSBűB…
557 …AB_��?���@�������������??bAB_��?���@P;KBE��@���@L�AB���@���@�������������?DSB�>�@���@[^YB�KA���@…
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 292 // SLREX,DMB,DSB
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 294 // SLREX,DMB,DSB
|
| D | AArch64SchedFalkorDetails.td | 1245 def : InstRW<[FalkorWr_1LD_0cyc], (instrs CLREX, DMB, DSB)>;
|
| /external/v8/src/codegen/arm64/ |
| D | constants-arm64.h | 787 DSB = MemBarrierFixed | 0x00000000, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 1106 66767U, // DSB
4326 0U, // DSB
7049 // DMB, DSB
9328 case ARM::DSB:
9334 // (DSB 12)
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 824 DSB = MemBarrierFixed | 0x00000000, enumerator
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/ |
| D | ptmv1_0x13.txt | 44 Instruction 31 S:0xC0018DB8 0xF3BF8F4F 0 DSB false
2728 Instruction 2639 S:0xC003C0BC 0xF3BF8F4F 0 DSB false
3427 Instruction 3316 S:0xC003CA0A 0xF3BF8F4F 0 DSB false
4627 Instruction 4482 S:0xC002D9D0 0xF3BF8F4F 0 DSB false
4840 Instruction 4683 S:0xC00171BE 0xF3BF8F4F 0 DSB false
4847 Instruction 4690 S:0xC00171D6 0xF3BF8F4F 0 DSB false
4966 Instruction 4802 S:0xC00171BE 0xF3BF8F4F 0 DSB false
4973 Instruction 4809 S:0xC00171D6 0xF3BF8F4F 0 DSB false
5072 Instruction 4903 S:0xC00171BE 0xF3BF8F4F 0 DSB false
5079 Instruction 4910 S:0xC00171D6 0xF3BF8F4F 0 DSB false
[all …]
|
| D | etmv3_0x12.txt | 997 Instruction 972 S:0xC003CC60 0xF3BF8F4F 31 DSB false
1376 Instruction 1343 S:0xC00359FA 0xF3BF8F4F 45 DSB false
1774 Instruction 1729 S:0xC0025BE0 0xF3BF8F4F 31 DSB false
|
| /external/v8/src/diagnostics/arm64/ |
| D | disasm-arm64.cc | 1517 case DSB: { in VisitSystem()
|