1 /* 2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /** 8 * @file emmc_std.h 9 * @brief eMMC boot is expecting this header file 10 * 11 */ 12 13 #ifndef EMMC_STD_H 14 #define EMMC_STD_H 15 16 #include "emmc_hal.h" 17 18 /* ************************ HEADER (INCLUDE) SECTION *********************** */ 19 20 /* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ 21 #ifndef FALSE 22 #define FALSE 0U 23 #endif 24 #ifndef TRUE 25 #define TRUE 1U 26 #endif 27 28 /** @brief 64bit registers 29 **/ 30 #define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v)) 31 #define GETR_64(r) (*(volatile uint64_t *)(r)) 32 33 /** @brief 32bit registers 34 **/ 35 #define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v)) 36 #define GETR_32(r) (*(volatile uint32_t *)(r)) 37 38 /** @brief 16bit registers 39 */ 40 #define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v)) 41 #define GETR_16(r) (*(volatile uint16_t *)(r)) 42 43 /** @brief 8bit registers 44 */ 45 #define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v)) 46 #define GETR_8(r) (*(volatile uint8_t *)(r)) 47 48 /** @brief CSD register Macros 49 */ 50 #define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y))) 51 52 #define EMMC_CID_MID() (EMMC_GET_CID(127, 120)) 53 #define EMMC_CID_CBX() (EMMC_GET_CID(113, 112)) 54 #define EMMC_CID_OID() (EMMC_GET_CID(111, 104)) 55 #define EMMC_CID_PNM1() (EMMC_GET_CID(103, 88)) 56 #define EMMC_CID_PNM2() (EMMC_GET_CID(87, 56)) 57 #define EMMC_CID_PRV() (EMMC_GET_CID(55, 48)) 58 #define EMMC_CID_PSN() (EMMC_GET_CID(47, 16)) 59 #define EMMC_CID_MDT() (EMMC_GET_CID(15, 8)) 60 #define EMMC_CID_CRC() (EMMC_GET_CID(7, 1)) 61 62 /** @brief CSD register Macros 63 */ 64 #define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y))) 65 66 #define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126)) 67 #define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122)) 68 #define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112)) 69 #define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104)) 70 #define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96)) 71 #define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84)) 72 #define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80)) 73 #define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79)) 74 #define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78)) 75 #define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77)) 76 #define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76)) 77 #define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62)) 78 #define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59)) 79 #define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56)) 80 #define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53)) 81 #define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50)) 82 #define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47)) 83 #define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42)) 84 #define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37)) 85 #define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32)) 86 #define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31)) 87 #define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29)) 88 #define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26)) 89 #define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22)) 90 #define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21)) 91 #define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16)) 92 #define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15)) 93 #define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14)) 94 #define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13)) 95 #define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12)) 96 #define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10)) 97 #define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8)) 98 #define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1)) 99 100 /** @brief for sector access 101 */ 102 #define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003 103 #define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */ 104 #define EMMC_SECTOR_SIZE 512 105 #define EMMC_BLOCK_LENGTH 512 106 #define EMMC_BLOCK_LENGTH_DW 128 107 #define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */ 108 109 /** @brief eMMC specification clock 110 */ 111 #define EMMC_CLOCK_SPEC_400K 400000UL /**< initialize clock 400KHz */ 112 #define EMMC_CLOCK_SPEC_20M 20000000UL /**< normal speed 20MHz */ 113 #define EMMC_CLOCK_SPEC_26M 26000000UL /**< high speed 26MHz */ 114 #define EMMC_CLOCK_SPEC_52M 52000000UL /**< high speed 52MHz */ 115 #define EMMC_CLOCK_SPEC_100M 100000000UL /**< high speed 100MHz */ 116 117 /** @brief EMMC driver error code. (extended HAL_MEMCARD_RETURN) 118 */ 119 typedef enum { 120 EMMC_ERR = 0, /**< unknown error */ 121 EMMC_SUCCESS, /**< OK */ 122 EMMC_ERR_FROM_DMAC, /**< DMAC allocation error */ 123 EMMC_ERR_FROM_DMAC_TRANSFER, /**< DMAC transfer error */ 124 EMMC_ERR_CARD_STATUS_BIT, /**< card status error. Non-masked error bit was set in the card status */ 125 EMMC_ERR_CMD_TIMEOUT, /**< command timeout error */ 126 EMMC_ERR_DATA_TIMEOUT, /**< data timeout error */ 127 EMMC_ERR_CMD_CRC, /**< command CRC error */ 128 EMMC_ERR_DATA_CRC, /**< data CRC error */ 129 EMMC_ERR_PARAM, /**< parameter error */ 130 EMMC_ERR_RESPONSE, /**< response error */ 131 EMMC_ERR_RESPONSE_BUSY, /**< response busy error */ 132 EMMC_ERR_TRANSFER, /**< data transfer error */ 133 EMMC_ERR_READ_SECTOR, /**< read sector error */ 134 EMMC_ERR_WRITE_SECTOR, /**< write sector error */ 135 EMMC_ERR_STATE, /**< state error */ 136 EMMC_ERR_TIMEOUT, /**< timeout error */ 137 EMMC_ERR_ILLEGAL_CARD, /**< illegal card */ 138 EMMC_ERR_CARD_BUSY, /**< Busy state */ 139 EMMC_ERR_CARD_STATE, /**< card state error */ 140 EMMC_ERR_SET_TRACE, /**< trace information error */ 141 EMMC_ERR_FROM_TIMER, /**< Timer error */ 142 EMMC_ERR_FORCE_TERMINATE, /**< Force terminate */ 143 EMMC_ERR_CARD_POWER, /**< card power fail */ 144 EMMC_ERR_ERASE_SECTOR, /**< erase sector error */ 145 EMMC_ERR_INFO2 /**< exec cmd error info2 */ 146 } EMMC_ERROR_CODE; 147 148 /** @brief Function number */ 149 #define EMMC_FUNCNO_NONE 0U 150 #define EMMC_FUNCNO_DRIVER_INIT 1U 151 #define EMMC_FUNCNO_CARD_POWER_ON 2U 152 #define EMMC_FUNCNO_MOUNT 3U 153 #define EMMC_FUNCNO_CARD_INIT 4U 154 #define EMMC_FUNCNO_HIGH_SPEED 5U 155 #define EMMC_FUNCNO_BUS_WIDTH 6U 156 #define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U 157 #define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U 158 #define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U 159 #define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U 160 #define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U 161 #define EMMC_FUNCNO_SET_CLOCK 12U 162 #define EMMC_FUNCNO_EXEC_CMD 13U 163 #define EMMC_FUNCNO_READ_SECTOR 14U 164 #define EMMC_FUNCNO_WRITE_SECTOR 15U 165 #define EMMC_FUNCNO_ERASE_SECTOR 16U 166 #define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U 167 /** @brief Response 168 */ 169 /** R1 */ 170 #define EMMC_R1_ERROR_MASK 0xFDBFE080U /* Type 'E' bit and bit14(must be 0). ignore bit22 */ 171 #define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */ 172 #define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */ 173 #define EMMC_R1_READY 0x00000100U /* bit8 */ 174 #define EMMC_R1_STATE_SHIFT 9 175 176 /** R4 */ 177 #define EMMC_R4_RCA_MASK 0xFFFF0000UL 178 #define EMMC_R4_STATUS 0x00008000UL 179 180 /** CSD */ 181 #define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */ 182 #define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0 183 #define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */ 184 #define EMMC_TRANSPEED_MULT_SHIFT 3 185 186 /** OCR */ 187 #define EMMC_HOST_OCR_VALUE 0x40FF8080 188 #define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */ 189 #define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */ 190 #define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L 191 #define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L 192 193 /** EXT_CSD */ 194 #define EMMC_EXT_CSD_S_CMD_SET 504 195 #define EMMC_EXT_CSD_INI_TIMEOUT_AP 241 196 #define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239 197 #define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238 198 #define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235 199 #define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234 200 #define EMMC_EXT_CSD_TRIM_MULT 232 201 #define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231 202 #define EMMC_EXT_CSD_SEC_ERASE_MULT 229 203 #define EMMC_EXT_CSD_BOOT_INFO 228 204 #define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226 205 #define EMMC_EXT_CSD_ACC_SIZE 225 206 #define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224 207 #define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223 208 #define EMMC_EXT_CSD_PEL_WR_SEC_C 222 209 #define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221 210 #define EMMC_EXT_CSD_S_C_VCC 220 211 #define EMMC_EXT_CSD_S_C_VCCQ 219 212 #define EMMC_EXT_CSD_S_A_TIMEOUT 217 213 #define EMMC_EXT_CSD_SEC_COUNT 215 214 #define EMMC_EXT_CSD_MIN_PERF_W_8_52 210 215 #define EMMC_EXT_CSD_MIN_PERF_R_8_52 209 216 #define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208 217 #define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207 218 #define EMMC_EXT_CSD_MIN_PERF_W_4_26 206 219 #define EMMC_EXT_CSD_MIN_PERF_R_4_26 205 220 #define EMMC_EXT_CSD_PWR_CL_26_360 203 221 #define EMMC_EXT_CSD_PWR_CL_52_360 202 222 #define EMMC_EXT_CSD_PWR_CL_26_195 201 223 #define EMMC_EXT_CSD_PWR_CL_52_195 200 224 #define EMMC_EXT_CSD_CARD_TYPE 196 225 #define EMMC_EXT_CSD_CSD_STRUCTURE 194 226 #define EMMC_EXT_CSD_EXT_CSD_REV 192 227 #define EMMC_EXT_CSD_CMD_SET 191 228 #define EMMC_EXT_CSD_CMD_SET_REV 189 229 #define EMMC_EXT_CSD_POWER_CLASS 187 230 #define EMMC_EXT_CSD_HS_TIMING 185 231 #define EMMC_EXT_CSD_BUS_WIDTH 183 232 #define EMMC_EXT_CSD_ERASED_MEM_CONT 181 233 #define EMMC_EXT_CSD_PARTITION_CONFIG 179 234 #define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178 235 #define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177 236 #define EMMC_EXT_CSD_ERASE_GROUP_DEF 175 237 #define EMMC_EXT_CSD_BOOT_WP 173 238 #define EMMC_EXT_CSD_USER_WP 171 239 #define EMMC_EXT_CSD_FW_CONFIG 169 240 #define EMMC_EXT_CSD_RPMB_SIZE_MULT 168 241 #define EMMC_EXT_CSD_RST_n_FUNCTION 162 242 #define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160 243 #define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159 244 #define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156 245 #define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155 246 #define EMMC_EXT_CSD_GP_SIZE_MULT 154 247 #define EMMC_EXT_CSD_ENH_SIZE_MULT 142 248 #define EMMC_EXT_CSD_ENH_START_ADDR 139 249 #define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134 250 251 #define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01 252 #define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02 253 #define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04 254 #define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08 255 #define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e 256 257 /** SWITCH (CMD6) argument */ 258 #define EXTCSD_ACCESS_BYTE (BIT25|BIT24) 259 #define EXTCSD_SET_BITS BIT24 260 261 #define HS_TIMING_ADD (185<<16) /* H'b9 */ 262 #define HS_TIMING_1 (1<<8) 263 #define HS_TIMING_HS200 (2<<8) 264 #define HS_TIMING_HS400 (3<<8) 265 266 #define BUS_WIDTH_ADD (183<<16) /* H'b7 */ 267 #define BUS_WIDTH_1 (0<<8) 268 #define BUS_WIDTH_4 (1<<8) 269 #define BUS_WIDTH_8 (2<<8) 270 #define BUS_WIDTH_4DDR (5<<8) 271 #define BUS_WIDTH_8DDR (6<<8) 272 273 #define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */ 274 #define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD) /**< H'03b90000 */ 275 276 #define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */ 277 #define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4) /**< H'03b70100 */ 278 #define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8) /**< H'03b70200 */ 279 #define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4DDR) /**< H'03b70500 */ 280 #define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8DDR) /**< H'03b70600 */ 281 #define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL /**< Partition config = 0x00 */ 282 283 #define TIMING_HIGH_SPEED 1UL 284 #define EMMC_BOOT_PARTITION_EN_MASK 0x38U 285 #define EMMC_BOOT_PARTITION_EN_SHIFT 3U 286 287 /** Bus width */ 288 #define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT 289 #define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT 290 #define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT 291 292 /** for st_mmc_base */ 293 #define EMMC_MAX_RESPONSE_LENGTH 17 294 #define EMMC_MAX_CID_LENGTH 16 295 #define EMMC_MAX_CSD_LENGTH 16 296 #define EMMC_MAX_EXT_CSD_LENGTH 512U 297 #define EMMC_RES_REG_ALIGNED 4U 298 #define EMMC_BUF_REG_ALIGNED 8U 299 300 /** @brief for TAAC mask 301 */ 302 #define TAAC_TIME_UNIT_MASK (0x07) 303 #define TAAC_MULTIPLIER_FACTOR_MASK (0x0F) 304 305 /* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ 306 307 /** @brief Partition id 308 */ 309 typedef enum { 310 PARTITION_ID_USER = 0x0, /**< User Area */ 311 PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */ 312 PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */ 313 PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */ 314 PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */ 315 PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */ 316 PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */ 317 PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */ 318 PARTITION_ID_MASK = 0x7 /**< [2:0] */ 319 } EMMC_PARTITION_ID; 320 321 /** @brief card state in R1 response [12:9] 322 */ 323 typedef enum { 324 EMMC_R1_STATE_IDLE = 0, 325 EMMC_R1_STATE_READY, 326 EMMC_R1_STATE_IDENT, 327 EMMC_R1_STATE_STBY, 328 EMMC_R1_STATE_TRAN, 329 EMMC_R1_STATE_DATA, 330 EMMC_R1_STATE_RCV, 331 EMMC_R1_STATE_PRG, 332 EMMC_R1_STATE_DIS, 333 EMMC_R1_STATE_BTST, 334 EMMC_R1_STATE_SLEP 335 } EMMC_R1_STATE; 336 337 typedef enum { 338 ESTATE_BEGIN = 0, 339 ESTATE_ISSUE_CMD, 340 ESTATE_NON_RESP_CMD, 341 ESTATE_RCV_RESP, 342 ESTATE_RCV_RESPONSE_BUSY, 343 ESTATE_CHECK_RESPONSE_COMPLETE, 344 ESTATE_DATA_TRANSFER, 345 ESTATE_DATA_TRANSFER_COMPLETE, 346 ESTATE_ACCESS_END, 347 ESTATE_TRANSFER_ERROR, 348 ESTATE_ERROR, 349 ESTATE_END 350 } EMMC_INT_STATE; 351 352 /** @brief eMMC boot driver error information 353 */ 354 typedef struct { 355 uint16_t num; /**< error no */ 356 uint16_t code; /**< error code */ 357 volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */ 358 volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */ 359 volatile uint32_t status1;/**< SD_ERR_STS1 register value. (hardware dependence) */ 360 volatile uint32_t status2;/**< SD_ERR_STS2 register value. (hardware dependence) */ 361 volatile uint32_t dm_info1;/**< DM_CM_INFO1 register value. (hardware dependence) */ 362 volatile uint32_t dm_info2;/**< DM_CM_INFO2 register value. (hardware dependence) */ 363 } st_error_info; 364 365 /** @brief Command information 366 */ 367 typedef struct { 368 HAL_MEMCARD_COMMAND cmd; /**< Command information */ 369 uint32_t arg; /**< argument */ 370 HAL_MEMCARD_OPERATION dir; /**< direction */ 371 uint32_t hw; /**< H/W dependence. SD_CMD register value. */ 372 } st_command_info; 373 374 /** @brief MMC driver base 375 */ 376 typedef struct { 377 st_error_info error_info; /**< error information */ 378 st_command_info cmd_info; /**< command information */ 379 380 /* for data transfer */ 381 uint32_t *buff_address_virtual; /**< Dest or Src buff */ 382 uint32_t *buff_address_physical; /**< Dest or Src buff */ 383 HAL_MEMCARD_DATA_WIDTH bus_width; 384 /**< bus width */ 385 uint32_t trans_size; /**< transfer size for this command */ 386 uint32_t remain_size; /**< remain size for this command */ 387 uint32_t response_length; /**< response length for this command */ 388 uint32_t sector_size; /**< sector_size */ 389 390 /* clock */ 391 uint32_t base_clock; /**< MMC host controller clock */ 392 uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */ 393 uint32_t request_freq; /**< request freq [Hz] (400K, 26MHz, 52MHz, etc) */ 394 uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */ 395 396 /* state flag */ 397 HAL_MEMCARD_PRESENCE_STATUS card_present; 398 /**< presence status of the memory card */ 399 uint32_t card_power_enable; /**< True : Power ON */ 400 uint32_t clock_enable; /**< True : Clock ON */ 401 uint32_t initialize; /**< True : initialize complete. */ 402 uint32_t access_mode; /**< True : sector access, FALSE : byte access */ 403 uint32_t mount; /**< True : mount complete. */ 404 uint32_t selected; /**< True : selected card. */ 405 HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; 406 /**< 0: DMA, 1:PIO */ 407 uint32_t image_num; /**< loaded ISSW image No. ISSW have copy image. */ 408 EMMC_R1_STATE current_state; /**< card state */ 409 volatile uint32_t during_cmd_processing; /**< True : during command processing */ 410 volatile uint32_t during_transfer; /**< True : during transfer */ 411 volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/ 412 volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */ 413 volatile uint32_t force_terminate; /**< force terminate flag */ 414 volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */ 415 volatile uint32_t get_partition_access_flag; 416 /**< True : get partition access processing */ 417 418 EMMC_PARTITION_ID boot_partition_en; /**< Boot partition */ 419 EMMC_PARTITION_ID partition_access; /**< Current access partition */ 420 421 /* timeout */ 422 uint32_t hs_timing; /**< high speed */ 423 424 /* timeout */ 425 uint32_t data_timeout; /**< read and write data timeout.*/ 426 427 /* retry */ 428 uint32_t retries_after_fail; /**< how many times to try after fail, for instance sending command */ 429 430 /* interrupt */ 431 volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */ 432 volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */ 433 volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */ 434 volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */ 435 436 /* response */ 437 uint32_t *response; /**< pointer to buffer for executing command. */ 438 uint32_t r1_card_status; /**< R1 response data */ 439 uint32_t r3_ocr; /**< R3 response data */ 440 uint32_t r4_resp; /**< R4 response data */ 441 uint32_t r5_resp; /**< R5 response data */ 442 443 uint32_t low_clock_mode_enable; 444 /**< True : clock mode is low. (MMC clock = Max26MHz) */ 445 uint32_t reserved2; 446 uint32_t reserved3; 447 uint32_t reserved4; 448 449 /* CSD registers (4byte align) */ 450 uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /**< CSD */ 451 __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); 452 /* CID registers (4byte align) */ 453 uint8_t cid_data[EMMC_MAX_CID_LENGTH] /**< CID */ 454 __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); 455 /* EXT CSD registers (8byte align) */ 456 uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /**< EXT_CSD */ 457 __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED))); 458 /* Response registers (4byte align) */ 459 uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /**< other response */ 460 __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); 461 } st_mmc_base; 462 463 typedef int (*func) (void); 464 465 /* ********************** DECLARATION OF EXTERNAL DATA ********************* */ 466 467 /* ************************** FUNCTION PROTOTYPES ************************** */ 468 uint32_t emmc_get_csd_time(void); 469 470 #define MMC_DEBUG 471 /* ********************************* CODE ********************************** */ 472 473 /* ******************************** END ************************************ */ 474 #endif /* EMMC_STD_H */ 475