| /external/ltp/include/ |
| D | tst_common.h | 37 #define TST_RETRY_FUNC(FUNC, ERET) \ argument
38 TST_RETRY_FN_EXP_BACKOFF(FUNC, ERET, 1)
40 #define TST_RETRY_FN_EXP_BACKOFF(FUNC, ERET, MAX_DELAY) \ argument
46 if (tst_ret_ == ERET) \
55 ERET; \
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | mips-control-instructions.s | 11 # CHECK32-NEXT: # <MCInst #{{[0-9]+}} ERET
46 # CHECK64-NEXT: # <MCInst #{{[0-9]+}} ERET
|
| /external/llvm/test/MC/ARM/ |
| D | virtexts-thumb.s | 52 # SUBS PC, LR, #0 should have the same encoding as ERET.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | virtexts-thumb.s | 52 # SUBS PC, LR, #0 should have the same encoding as ERET.
|
| /external/arm-trusted-firmware/docs/components/ |
| D | secure-partition-manager-design.rst | 254 ERET instruction.
269 instruction (ERET) to S-EL0. Later, the Secure Partition issues an SVC
281 An ERET instruction is used by TF-A to return to S-EL0 with the result of the
380 used as the target of the ERET instruction to start initialisation of the Secure
452 SPM will invoke the entry point of a service by executing an ERET instruction.
578 syndrome information can be used to return control through an ERET
|
| D | exception-handling.rst | 395 through an ``ERET``, resumes execution before the interrupt occurred.
403 enter a lower EL upon the next ``ERET``.
405 #. Through the ensuing ``ERET`` from runtime firmware, execution is delegated
|
| /external/u-boot/arch/arm/cpu/armv7/ |
| D | nonsec_virt.S | 104 movs pc, lr @ ERET to non-secure
|
| /external/u-boot/arch/arm/cpu/armv8/ |
| D | Kconfig | 88 bool "ARMv8 secure monitor firmware ERET address byteorder swap"
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 533 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET)); in expandERet()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 691 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET)); in expandERet()
|
| D | MipsScheduleP5600.td | 67 DERET, ERET, ERETNC, J, JR, JR_HB,
|
| /external/OpenCSD/decoder/tests/snapshots/TC2/pkt_proc_logs/ |
| D | trc_pkt_lister_0x13.ppl | 588 Idx:28058; ID:13; ERET : Exception return packet;
1004 Idx:29198; ID:13; ERET : Exception return packet;
1026 Idx:29302; ID:13; ERET : Exception return packet;
1809 Idx:32420; ID:13; ERET : Exception return packet;
|
| D | trc_pkt_lister-dcd-0x13.ppl | 1160 Idx:28058; ID:13; [0x76 ]; ERET : Exception return packet;
1974 Idx:29198; ID:13; [0x76 ]; ERET : Exception return packet;
2018 Idx:29302; ID:13; [0x76 ]; ERET : Exception return packet;
3571 Idx:32420; ID:13; [0x76 ]; ERET : Exception return packet;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 648 {DBGFIELD("ERET") 1, false, false, 3, 2, 1, 1, 0, 0}, // #373
1668 {DBGFIELD("ERET") 1, false, false, 38, 3, 1, 1, 0, 0}, // #373
|
| D | MipsGenMCCodeEmitter.inc | 1317 UINT64_C(1107296280), // ERET
2655 case Mips::ERET:
9043 Feature_HasStdEnc | Feature_HasMips3_32 | Feature_NotInMicroMips | 0, // ERET = 1304
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenSubtargetInfo.inc | 2191 {DBGFIELD("ERET") 1, false, false, 3, 1, 4, 1, 0, 0}, // #675
3177 {DBGFIELD("ERET") 1, false, false, 2, 1, 4, 1, 0, 0}, // #675
4163 {DBGFIELD("ERET") 1, false, false, 162, 3, 0, 1, 0, 0}, // #675
5149 {DBGFIELD("ERET") 1, false, false, 109, 2, 4, 1, 0, 0}, // #675
6135 {DBGFIELD("ERET") 1, false, false, 384, 2, 4, 1, 0, 0}, // #675
7121 {DBGFIELD("ERET") 3, false, false, 605, 5, 5, 1, 0, 0}, // #675
8107 {DBGFIELD("ERET") 3, false, false, 784, 3, 5, 1, 0, 0}, // #675
9093 {DBGFIELD("ERET") 1, false, false, 3, 1, 4, 1, 0, 0}, // #675
10079 {DBGFIELD("ERET") 2, false, false, 802, 3, 4, 1, 0, 0}, // #675
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 1111 838971U, // ERET
4331 0U, // ERET
7032 // BX_RET, ERET, FMSTAT, MOVPCLR, t2CLREX, t2DCPS1, t2DCPS2, t2DCPS3, t2S...
7183 // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R...
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 1261 def : InstRW<[FalkorWr_2LD_1Z_3cyc], (instrs ERET)>;
|
| D | AArch64SchedKryoDetails.td | 586 (instrs ERET)>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 128 "(t2)?CPS[123]p$", "(t2)?DBG$", "(t2)?DMB$", "(t2)?DSB$", "ERET$",
|
| D | ARMInstrThumb2.td | 3852 // ERET - Return from exception in Hypervisor mode.
3853 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 651 9195U, // ERET
2365 0U, // ERET
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedKryoDetails.td | 586 (instrs ERET)>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3862 // ERET - Return from exception in Hypervisor mode.
3863 // B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that
|
| /external/capstone/arch/AArch64/ |
| D | AArch64GenAsmWriter.inc | 317 2724U, // ERET
2709 0U, // ERET
5209 // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET
|