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Searched refs:EndIdx (Results 1 – 21 of 21) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineOutliner.cpp143 unsigned *EndIdx = nullptr; member
196 assert(*EndIdx != EmptyIdx && "EndIdx is undefined!"); in size()
200 return *EndIdx - StartIdx + 1; in size()
203 SuffixTreeNode(unsigned StartIdx, unsigned *EndIdx, SuffixTreeNode *Link, in SuffixTreeNode()
205 : StartIdx(StartIdx), EndIdx(EndIdx), Link(Link), Parent(Parent) {} in SuffixTreeNode()
309 unsigned EndIdx, unsigned Edge) { in insertInternalNode() argument
311 assert(StartIdx <= EndIdx && "String can't start after it ends!"); in insertInternalNode()
315 unsigned *E = new (InternalEndIdxAllocator) unsigned(EndIdx); in insertInternalNode()
376 unsigned extend(unsigned EndIdx, unsigned SuffixesToAdd) { in extend() argument
384 Active.Idx = EndIdx; in extend()
[all …]
DPostRASchedulerList.cpp161 void setEndIndex(unsigned EndIdx) { EndIndex = EndIdx; } in setEndIndex() argument
DStackColoring.cpp868 SlotIndex EndIdx = Indexes->getMBBEndIdx(&MBB); in calculateLiveIntervals() local
870 Intervals[i]->addSegment(LiveInterval::Segment(Starts[i], EndIdx, VNI)); in calculateLiveIntervals()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp862 unsigned StartIdx, EndIdx; member
875 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false), in BitGroup()
1081 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 && in collectBitGroups()
1085 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx; in collectBitGroups()
1136 if (BG.StartIdx <= BG.EndIdx) { in assignRepl32BitGroups()
1137 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) { in assignRepl32BitGroups()
1150 for (unsigned i = 0; i <= BG.EndIdx; ++i) { in assignRepl32BitGroups()
1162 if (BG.StartIdx < 32 && BG.EndIdx < 32) { in assignRepl32BitGroups()
1173 " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n"); in assignRepl32BitGroups()
1185 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) { in assignRepl32BitGroups()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp302 int EndIdx = NotSet; in trySequenceOfOnes() local
312 EndIdx = Idx; in trySequenceOfOnes()
316 if (StartIdx == NotSet || EndIdx == NotSet) in trySequenceOfOnes()
327 if (StartIdx > EndIdx) { in trySequenceOfOnes()
328 std::swap(StartIdx, EndIdx); in trySequenceOfOnes()
343 if ((Idx < StartIdx || EndIdx < Idx) && Chunk != Outside) { in trySequenceOfOnes()
354 } else if (Idx > StartIdx && Idx < EndIdx && Chunk != Inside) { in trySequenceOfOnes()
DAArch64InstrInfo.cpp756 for (unsigned OpIdx = 0, EndIdx = Instr.getNumOperands(); OpIdx < EndIdx; in UpdateOperandRegClass() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp272 int EndIdx = NotSet; in trySequenceOfOnes() local
282 EndIdx = Idx; in trySequenceOfOnes()
286 if (StartIdx == NotSet || EndIdx == NotSet) in trySequenceOfOnes()
297 if (StartIdx > EndIdx) { in trySequenceOfOnes()
298 std::swap(StartIdx, EndIdx); in trySequenceOfOnes()
313 if ((Idx < StartIdx || EndIdx < Idx) && Chunk != Outside) { in trySequenceOfOnes()
324 } else if (Idx > StartIdx && Idx < EndIdx && Chunk != Inside) { in trySequenceOfOnes()
DAArch64InstrInfo.cpp1183 for (unsigned OpIdx = 0, EndIdx = Instr.getNumOperands(); OpIdx < EndIdx; in UpdateOperandRegClass() local
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp1565 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1566 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1569 for (; SuperIdx != EndIdx; ++SuperIdx) { in pruneUnitSets()
1590 if (SuperIdx == EndIdx) in pruneUnitSets()
1659 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { in computeRegUnitSets() local
1667 SearchIdx != EndIdx; ++SearchIdx) { in computeRegUnitSets()
1843 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) in computeDerivedInfo() local
1848 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) in computeDerivedInfo() local
1856 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { in computeDerivedInfo() local
DSubtargetEmitter.cpp959 for (unsigned UseIdx = 0, EndIdx = Reads.size(); in GenSchedClassTables() local
960 UseIdx != EndIdx; ++UseIdx) { in GenSchedClassTables()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.cpp1768 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1769 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1772 for (; SuperIdx != EndIdx; ++SuperIdx) { in pruneUnitSets()
1793 if (SuperIdx == EndIdx) in pruneUnitSets()
1859 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { in computeRegUnitSets() local
1867 SearchIdx != EndIdx; ++SearchIdx) { in computeRegUnitSets()
2042 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) in computeDerivedInfo() local
2047 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) in computeDerivedInfo() local
2055 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { in computeDerivedInfo() local
DSubtargetEmitter.cpp1156 for (unsigned UseIdx = 0, EndIdx = Reads.size(); in GenSchedClassTables() local
1157 UseIdx != EndIdx; ++UseIdx) { in GenSchedClassTables()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp179 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; in getInstrMappingImpl() local
409 EndIdx = OpdMapper.getInstrMapping().getNumOperands(); in applyDefaultMapping() local
410 OpIdx != EndIdx; ++OpIdx) { in applyDefaultMapping()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1119 unsigned StartIdx, EndIdx; member
1132 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false), in BitGroup()
1370 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 && in collectBitGroups()
1374 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx; in collectBitGroups()
1427 if (BG.StartIdx <= BG.EndIdx) { in assignRepl32BitGroups()
1428 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) { in assignRepl32BitGroups()
1441 for (unsigned i = 0; i <= BG.EndIdx; ++i) { in assignRepl32BitGroups()
1467 if (BG.StartIdx < 32 && BG.EndIdx < 32) { in assignRepl32BitGroups()
1478 << BG.StartIdx << ", " << BG.EndIdx << "]\n"); in assignRepl32BitGroups()
1490 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) { in assignRepl32BitGroups()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/DebugInfo/DWARF/
DDWARFUnit.cpp581 for (size_t I = getDIEIndex(Die) + 1, EndIdx = DieArray.size(); I < EndIdx; in getSibling() local
624 for (size_t I = getDIEIndex(Die) + 1, EndIdx = DieArray.size(); I < EndIdx; in getLastChild() local
/external/llvm/lib/CodeGen/
DPostRASchedulerList.cpp161 void setEndIndex(unsigned EndIdx) { EndIndex = EndIdx; } in setEndIndex() argument
/external/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp910 unsigned EndIdx = Mask.back(); in isShuffleExtractingFromLHS() local
911 if (BegIdx > EndIdx || EndIdx >= LHSElems || EndIdx - BegIdx != MaskElems - 1) in isShuffleExtractingFromLHS()
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp338 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; in applyDefaultMapping() local
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp1134 unsigned EndIdx = Mask.back(); in isShuffleExtractingFromLHS() local
1135 if (BegIdx > EndIdx || EndIdx >= LHSElems || EndIdx - BegIdx != MaskElems - 1) in isShuffleExtractingFromLHS()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp8594 int EndIdx = in lowerVectorShuffleAsBroadcast() local
8596 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) { in lowerVectorShuffleAsBroadcast()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp10945 int EndIdx = in lowerVectorShuffleAsBroadcast() local
10947 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) { in lowerVectorShuffleAsBroadcast()