| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 4392 unsigned ExtOp, TruncOp; in PromoteNode() local
4394 ExtOp = ISD::BITCAST; in PromoteNode()
4401 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4405 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
4409 ExtOp = ISD::ZERO_EXTEND; in PromoteNode()
4415 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); in PromoteNode()
4416 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
4425 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND in PromoteNode() local
4427 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); in PromoteNode()
4428 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
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| D | DAGCombiner.cpp | 11657 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
11659 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 4940 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
4943 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
4947 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
4949 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
4952 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
4954 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
4957 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
4983 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
4985 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
4987 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
[all …]
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| D | X86InstrAVX512.td | 9326 multiclass AVX512_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
9393 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
9395 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
9397 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
9401 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
9403 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
9405 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
9407 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
9410 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
9412 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
[all …]
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| D | X86ISelLowering.cpp | 15492 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
15495 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector()
32285 SDValue ExtOp = DAG.getNode(OpCode, dl, MVT::i32, SrcOp, in combineExtractWithShuffle() local
32287 return DAG.getZExtOrTrunc(ExtOp, dl, VT); in combineExtractWithShuffle()
39571 unsigned ExtOp = InOpcode == X86ISD::VZEXT ? ISD::ZERO_EXTEND_VECTOR_INREG in combineExtractSubvector() local
39573 return DAG.getNode(ExtOp, SDLoc(N), OpVT, InVec.getOperand(0)); in combineExtractSubvector()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 4095 unsigned ExtOp, TruncOp; in PromoteNode() local
4097 ExtOp = ISD::BITCAST; in PromoteNode()
4101 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4105 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); in PromoteNode()
4106 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
4113 unsigned ExtOp, TruncOp; in PromoteNode() local
4116 ExtOp = ISD::BITCAST; in PromoteNode()
4119 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4122 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4127 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
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| D | DAGCombiner.cpp | 9104 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
9106 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 5834 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5837 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5841 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5843 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5846 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5848 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5851 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5877 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5879 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5881 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
[all …]
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| D | X86ISelLowering.cpp | 12539 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
12542 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector()
14617 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op); in EmitTest() local
14618 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp, in EmitTest()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstExtenders.cpp | 1530 MachineOperand ExtOp(EV); in insertInitializer() local
1541 .add(ExtOp); in insertInitializer()
1547 .add(ExtOp); in insertInitializer()
1552 .add(ExtOp) in insertInitializer()
1558 .add(ExtOp); in insertInitializer()
1565 .add(ExtOp) in insertInitializer()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCodeGenPrepare.cpp | 384 Value *ExtOp = Builder.CreateZExt(I.getOperand(0), I32Ty); in promoteUniformBitreverseToI32() local
385 Value *ExtRes = Builder.CreateCall(I32, { ExtOp }); in promoteUniformBitreverseToI32()
|
| D | SIISelLowering.cpp | 6990 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in performIntMed3ImmCombine() local
6992 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0)); in performIntMed3ImmCombine()
6993 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1)); in performIntMed3ImmCombine()
6994 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1); in performIntMed3ImmCombine()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3007 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3013 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3097 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
3102 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3103 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3110 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3115 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3164 SDNode OpNode, SDNode ExtOp, bit Commutable>
3169 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3675 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
[all …]
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| D | ARMISelLowering.cpp | 9974 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineBUILD_VECTORToVPADDL() local
9975 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineBUILD_VECTORToVPADDL()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2916 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2922 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3006 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
3011 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3012 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3019 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3024 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3073 SDNode OpNode, SDNode ExtOp, bit Commutable>
3078 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3584 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
[all …]
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| D | ARMISelLowering.cpp | 8806 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineToVPADDL() local
8807 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineToVPADDL()
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 1244 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
1245 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in widenLoopCompare()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 1365 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
1366 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in widenLoopCompare()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 2186 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments() local
2188 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr, in LowerFormalArguments()
2312 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments() local
2315 ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue), in LowerFormalArguments()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 5763 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
5764 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
6326 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
6327 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_Darwin()
12011 ConstantSDNode *ExtOp = dyn_cast<ConstantSDNode>(Extract.getOperand(1)); in combineBVOfVecSExt() local
12012 if (!ExtOp) in combineBVOfVecSExt()
12015 Index = ExtOp->getZExtValue(); in combineBVOfVecSExt()
|
| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 3782 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument
3786 if (ExtOp) in packTBLDVectorList()
3787 TblOps.push_back(ExtOp); in packTBLDVectorList()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 5201 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
5202 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
5769 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
5770 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_Darwin()
|