| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 27 # Same with FCVTZS and FCVTZU.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 27 # Same with FCVTZS and FCVTZU.
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1603 FCVTZS = FPIntegerConvertFixed | 0x00180000, enumerator
1604 FCVTZS_wh = FCVTZS | FP16,
1605 FCVTZS_xh = FCVTZS | SixtyFourBits | FP16,
1606 FCVTZS_ws = FCVTZS,
1607 FCVTZS_xs = FCVTZS | SixtyFourBits,
1608 FCVTZS_wd = FCVTZS | FP64,
1609 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
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| D | disasm-aarch64.cc | 2650 FORMAT(FCVTZS, "fcvtzs") in VisitNEON2RegMiscFP16()
4195 FORMAT(FCVTZS, "fcvtzs") in VisitNEONScalar2RegMiscFP16()
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| D | assembler-aarch64.cc | 3132 Emit(SF(rd) | FPType(vn) | FCVTZS | Rn(vn) | Rd(rd)); in NEON_FP2REGMISC_FCVT_LIST()
|
| /external/v8/src/codegen/arm64/ |
| D | constants-arm64.h | 1293 FCVTZS = FPIntegerConvertFixed | 0x00180000, enumerator
1294 FCVTZS_ws = FCVTZS,
1295 FCVTZS_xs = FCVTZS | SixtyFourBits,
1296 FCVTZS_wd = FCVTZS | FP64,
1297 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
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| D | assembler-arm64.cc | 2955 Emit(SF(rd) | FPType(vn) | FCVTZS | Rn(vn) | Rd(rd)); in fcvtzs()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 92 #define FCVTZS 0x9e780000 macro
1370 FAIL_IF(push_inst(compiler, (FCVTZS ^ inv_bits) | RD(dst_r) | VN(src))); in sljit_emit_fop1_conv_sw_from_f64()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2501 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2503 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2528 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">;
2546 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
2819 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
3359 defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">;
4678 defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">;
4752 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2782 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2784 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2809 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">;
2827 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
3083 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
3636 defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">;
5013 defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">;
5122 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3793 ### FCVTZS ### subsection
3800 ### FCVTZS ### subsection
|