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Searched refs:FMUL_D (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td95 def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">;
96 def : FPALUDDynFrmAlias<FMUL_D, "fmul.d">;
227 def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h750 #define FMUL_D(a) CHOICE(fmull a, fmull a, fmuld a) macro
1463 #define FMUL_D(a) fmul D_(a) macro
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc771 33573295U, // FMUL_D
2485 0U, // FMUL_D
DMipsGenDisassemblerTables.inc2682 /* 9247 */ MCD_OPC_Decode, 242, 5, 117, // Opcode: FMUL_D
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc1459 UINT64_C(2023751707), // FMUL_D
7289 case Mips::FMUL_D:
9185 Feature_HasStdEnc | Feature_HasMSA | 0, // FMUL_D = 1446
DMipsGenAsmWriter.inc2674 268454781U, // FMUL_D
5305 0U, // FMUL_D
DMipsGenFastISel.inc1607 return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenGlobalISel.inc14353 …4] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA1…
14354 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D,
DMipsGenInstrInfo.inc1461 FMUL_D = 1446,
5506 …6, 3, 1, 4, 634, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1446 = FMUL_D
DMipsGenDisassemblerTables.inc5141 /* 11854 */ MCD::OPC_Decode, 166, 11, 253, 1, // Opcode: FMUL_D
DMipsGenAsmMatcher.inc6270 …{ 4591 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Fea…
DMipsGenDAGISel.inc28119 /* 52845*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_D), 0,
28122 … // Dst: (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3079 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3086 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;