Searched refs:FPZero (Results 1 – 8 of 8) sorted by relevance
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 3119 WriteWRegister(dst, FPToInt32(ReadHRegister(src), FPZero)); in VisitFPIntegerConvert()
3122 WriteXRegister(dst, FPToInt64(ReadHRegister(src), FPZero)); in VisitFPIntegerConvert()
3125 WriteWRegister(dst, FPToInt32(ReadSRegister(src), FPZero)); in VisitFPIntegerConvert()
3128 WriteXRegister(dst, FPToInt64(ReadSRegister(src), FPZero)); in VisitFPIntegerConvert()
3131 WriteWRegister(dst, FPToInt32(ReadDRegister(src), FPZero)); in VisitFPIntegerConvert()
3134 WriteXRegister(dst, FPToInt64(ReadDRegister(src), FPZero)); in VisitFPIntegerConvert()
3137 WriteWRegister(dst, FPToUInt32(ReadHRegister(src), FPZero)); in VisitFPIntegerConvert()
3140 WriteXRegister(dst, FPToUInt64(ReadHRegister(src), FPZero)); in VisitFPIntegerConvert()
3143 WriteWRegister(dst, FPToUInt32(ReadSRegister(src), FPZero)); in VisitFPIntegerConvert()
3146 WriteXRegister(dst, FPToUInt64(ReadSRegister(src), FPZero)); in VisitFPIntegerConvert()
[all …]
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| D | logic-aarch64.cc | 4044 case FPZero: { in FPRoundIntCommon()
5262 case FPZero: in FPRecipEstimate()
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| /external/v8/src/execution/arm64/ |
| D | simulator-arm64.cc | 2736 set_wreg(dst, FPToInt32(sreg(src), FPZero)); in VisitFPIntegerConvert()
2739 set_xreg(dst, FPToInt64(sreg(src), FPZero)); in VisitFPIntegerConvert()
2742 set_wreg(dst, FPToInt32(dreg(src), FPZero)); in VisitFPIntegerConvert()
2745 set_xreg(dst, FPToInt64(dreg(src), FPZero)); in VisitFPIntegerConvert()
2748 set_wreg(dst, FPToUInt32(sreg(src), FPZero)); in VisitFPIntegerConvert()
2751 set_xreg(dst, FPToUInt64(sreg(src), FPZero)); in VisitFPIntegerConvert()
2754 set_wreg(dst, FPToUInt32(dreg(src), FPZero)); in VisitFPIntegerConvert()
2757 set_xreg(dst, FPToUInt64(dreg(src), FPZero)); in VisitFPIntegerConvert()
3002 fpcr_rounding = FPZero; in VisitFPDataProcessing1Source()
3839 fpcr_rounding = FPZero; in VisitNEON2RegMisc()
[all …]
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| D | simulator-logic-arm64.cc | 3190 case FPZero: { in FPRoundInt()
4037 case FPZero: in FPRecipEstimate()
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| /external/v8/src/codegen/arm64/ |
| D | instructions-arm64.h | 71 FPZero = 0x3, enumerator
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| /external/vixl/src/ |
| D | utils-vixl.h | 1015 FPZero = 0x3, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 18332 SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); in buildSqrtEstimateImpl() local
18335 Est = DAG.getNode(SelOpcode, DL, VT, IsDenorm, FPZero, Est); in buildSqrtEstimateImpl()
18341 SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); in buildSqrtEstimateImpl() local
18342 SDValue IsZero = DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); in buildSqrtEstimateImpl()
18343 Est = DAG.getNode(SelOpcode, DL, VT, IsZero, FPZero, Est); in buildSqrtEstimateImpl()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 5300 SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); in getSqrtEstimate() local
5301 SDValue Eq = DAG.getSetCC(DL, CCVT, Operand, FPZero, ISD::SETEQ); in getSqrtEstimate()
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