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Searched refs:FSL_CHASSIS3_RCWSR12_REGSR (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/board/freescale/lx2160a/
Dlx2160a.c205 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in esdhc_dspi_status_fixup()
241 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in esdhc_dspi_status_fixup()
409 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in config_board_mux()
448 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) in config_board_mux()
/external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
Dimmap_lsch3.h399 #define FSL_CHASSIS3_RCWSR12_REGSR 12 macro