Searched refs:FSL_CHASSIS3_SRDS1_REGSR (Results 1 – 4 of 4) sorted by relevance
473 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in initialize_dpmac_to_slot()526 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in ls1088a_handle_phy_interface_sgmii()578 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in ls1088a_handle_phy_interface_qsgmii()617 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in ls1088a_handle_phy_interface_xsgmii()642 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in ls1088a_handle_phy_interface_rgmii()
30 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in board_eth_init()
375 #define FSL_CHASSIS3_SRDS1_REGSR 29 macro396 #define FSL_CHASSIS3_SRDS1_REGSR 29 macro422 #define FSL_CHASSIS3_SRDS1_REGSR 29 macro429 #define FSL_CHASSIS3_SRDS1_REGSR 29 macro
92 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); in serdes_get_first_lane()397 u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); in setup_serdes_volt()581 FSL_CHASSIS3_SRDS1_REGSR, in fsl_serdes_init()