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Searched refs:FSUB (Results 1 – 25 of 135) sorted by relevance

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/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dblend_jit.cpp84 out[0] = out[1] = out[2] = VMINPS(src[3], FSUB(VIMMED1(1.0f), dst[3])); in GenerateBlendFactor()
109 out[0] = FSUB(VIMMED1(1.0f), src[0]); in GenerateBlendFactor()
110 out[1] = FSUB(VIMMED1(1.0f), src[1]); in GenerateBlendFactor()
111 out[2] = FSUB(VIMMED1(1.0f), src[2]); in GenerateBlendFactor()
112 out[3] = FSUB(VIMMED1(1.0f), src[3]); in GenerateBlendFactor()
115 out[0] = out[1] = out[2] = out[3] = FSUB(VIMMED1(1.0f), src[3]); in GenerateBlendFactor()
118 out[0] = out[1] = out[2] = out[3] = FSUB(VIMMED1(1.0f), dst[3]); in GenerateBlendFactor()
121 out[0] = FSUB(VIMMED1(1.0f), dst[0]); in GenerateBlendFactor()
122 out[1] = FSUB(VIMMED1(1.0f), dst[1]); in GenerateBlendFactor()
123 out[2] = FSUB(VIMMED1(1.0f), dst[2]); in GenerateBlendFactor()
[all …]
/external/apache-commons-bcel/src/main/java/org/apache/bcel/generic/
DFSUB.java26 public class FSUB extends ArithmeticInstruction { class
30 public FSUB() { in FSUB() method in FSUB
31 super(org.apache.bcel.Const.FSUB); in FSUB()
DInstructionConstants.java95 ArithmeticInstruction FSUB = new FSUB(); field
230 INSTRUCTIONS[Const.FSUB] = FSUB; in Clinit()
DInstructionConst.java94 public static final ArithmeticInstruction FSUB = new FSUB(); field in InstructionConst
225 INSTRUCTIONS[Const.FSUB] = FSUB;
DArithmeticInstruction.java64 case Const.FSUB: in getType()
DVisitor.java279 void visitFSUB( FSUB obj ); in visitFSUB()
DEmptyVisitor.java443 public void visitFSUB( final FSUB obj ) { in visitFSUB()
DInstructionFactory.java384 return InstructionConst.FSUB; in createBinaryFloatOp()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-fneg.mir27 ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[C]], [[COPY]]
28 ; CHECK: $s0 = COPY [[FSUB]](s32)
44 ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[C]], [[COPY]]
45 ; CHECK: $d0 = COPY [[FSUB]](s64)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dlegalize-fsub-scalar.mir41 ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[TRUNC]], [[TRUNC1]]
42 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FSUB]](s32)
80 ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[TRUNC]], [[TRUNC1]]
81 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[FSUB]](s64)
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h241 FADD, FSUB, FMUL, FDIV, FREM, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h260 FADD, FSUB, FMUL, FDIV, FREM, enumerator
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu.h195 A_ALU2(FSUB)
Dvc4_qpu_emit.c259 A(FSUB), in vc4_generate_code_block()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUTargetTransformInfo.cpp165 case ISD::FSUB: in getArithmeticInstrCost()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp331 case ISD::FSUB: in LegalizeOp()
727 case ISD::FSUB: in Expand()
1067 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { in ExpandFNEG()
1071 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(), in ExpandFNEG()
DSelectionDAGBuilder.cpp2662 visitBinary(I, ISD::FSUB); in visitFSub()
4401 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in getLimitedPrecisionExp2()
4538 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
4555 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
4561 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
4580 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
4586 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
4592 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, in expandLog()
4634 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
4651 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd in getArithmeticInstrCost()
491 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
495 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
635 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
636 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
695 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
696 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
697 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
698 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp272 case ISD::FSUB: in LegalizeOp()
1020 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { in ExpandFNEG()
1024 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(), in ExpandFNEG()
DSelectionDAGBuilder.cpp2464 visitBinary(I, ISD::FSUB); in visitFSub()
4164 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in getLimitedPrecisionExp2()
4302 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
4319 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
4325 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
4344 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
4350 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
4356 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, in expandLog()
4399 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
4416 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
[all …]
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h1441 X86_INTRINSIC_DATA(avx512_mask_sub_pd_128, INTR_TYPE_2OP_MASK, ISD::FSUB, 0),
1442 X86_INTRINSIC_DATA(avx512_mask_sub_pd_256, INTR_TYPE_2OP_MASK, ISD::FSUB, 0),
1443 X86_INTRINSIC_DATA(avx512_mask_sub_pd_512, INTR_TYPE_2OP_MASK, ISD::FSUB,
1445 X86_INTRINSIC_DATA(avx512_mask_sub_ps_128, INTR_TYPE_2OP_MASK, ISD::FSUB, 0),
1446 X86_INTRINSIC_DATA(avx512_mask_sub_ps_256, INTR_TYPE_2OP_MASK, ISD::FSUB, 0),
1447 X86_INTRINSIC_DATA(avx512_mask_sub_ps_512, INTR_TYPE_2OP_MASK, ISD::FSUB,
1449 X86_INTRINSIC_DATA(avx512_mask_sub_sd_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FSUB,
1451 X86_INTRINSIC_DATA(avx512_mask_sub_ss_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FSUB,
/external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/
DLabelFlowAnalyzerTest.java194 testInsn(FSUB, true); in testInsn()
/external/apache-commons-bcel/src/main/java/org/apache/bcel/
DConstants.java688 short FSUB = 102; field
DConst.java990 public static final short FSUB = 102; field in Const
/external/vixl/src/aarch64/
Dconstants-aarch64.h1511 FSUB = FPDataProcessing2SourceFixed | 0x00003000, enumerator
1512 FSUB_h = FSUB | FP16,
1513 FSUB_s = FSUB,
1514 FSUB_d = FSUB | FP64,

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