/external/u-boot/drivers/clk/sunxi/ |
D | clk_a10.c | 16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)), 17 [CLK_AHB_EHCI0] = GATE(0x060, BIT(1)), 18 [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)), 19 [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)), 20 [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)), 21 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), 22 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), 23 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), 24 [CLK_AHB_MMC3] = GATE(0x060, BIT(11)), 25 [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), [all …]
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D | clk_r40.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)), 20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 22 [CLK_BUS_SPI2] = GATE(0x060, BIT(22)), 23 [CLK_BUS_SPI3] = GATE(0x060, BIT(23)), 24 [CLK_BUS_OTG] = GATE(0x060, BIT(25)), 25 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [all …]
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D | clk_a31.c | 16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)), 20 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)), 21 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)), 22 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)), 23 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)), 24 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)), 25 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)), [all …]
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D | clk_h3.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), 20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)), 23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), 24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), 25 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)), [all …]
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D | clk_a64.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), 20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)), 23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), 24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), 25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [all …]
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D | clk_h6.c | 16 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), 17 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), 18 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), 19 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)), 20 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)), 21 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), 22 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)), 24 [CLK_SPI0] = GATE(0x940, BIT(31)), 25 [CLK_SPI1] = GATE(0x944, BIT(31)), 27 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)), [all …]
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D | clk_a80.c | 16 [CLK_SPI0] = GATE(0x430, BIT(31)), 17 [CLK_SPI1] = GATE(0x434, BIT(31)), 18 [CLK_SPI2] = GATE(0x438, BIT(31)), 19 [CLK_SPI3] = GATE(0x43c, BIT(31)), 21 [CLK_BUS_MMC] = GATE(0x580, BIT(8)), 22 [CLK_BUS_SPI0] = GATE(0x580, BIT(20)), 23 [CLK_BUS_SPI1] = GATE(0x580, BIT(21)), 24 [CLK_BUS_SPI2] = GATE(0x580, BIT(22)), 25 [CLK_BUS_SPI3] = GATE(0x580, BIT(23)), 27 [CLK_BUS_UART0] = GATE(0x594, BIT(16)), [all …]
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D | clk_a10s.c | 16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)), 17 [CLK_AHB_EHCI] = GATE(0x060, BIT(1)), 18 [CLK_AHB_OHCI] = GATE(0x060, BIT(2)), 19 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), 20 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), 21 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), 22 [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), 23 [CLK_AHB_SPI0] = GATE(0x060, BIT(20)), 24 [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), 25 [CLK_AHB_SPI2] = GATE(0x060, BIT(22)), [all …]
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D | clk_a83t.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), 20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)), 23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), 24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), 25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), [all …]
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D | clk_a23.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 20 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 21 [CLK_BUS_OTG] = GATE(0x060, BIT(24)), 22 [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), 23 [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), 25 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), 26 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [all …]
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D | clk_v3s.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 20 [CLK_BUS_OTG] = GATE(0x060, BIT(24)), 22 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), 23 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), 24 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), 26 [CLK_SPI0] = GATE(0x0a0, BIT(31)), 28 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
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/external/u-boot/arch/arm/cpu/armv7/bcm235xx/ |
D | clk-core.h | 95 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) 96 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) 97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) 98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) 99 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) 100 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) 102 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) 180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 181 FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ 182 FLAG(GATE, EXISTS), \ [all …]
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/external/u-boot/arch/arm/cpu/armv7/bcm281xx/ |
D | clk-core.h | 95 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) 96 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) 97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) 98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) 99 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) 100 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) 102 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) 180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 181 FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ 182 FLAG(GATE, EXISTS), \ [all …]
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/external/iptables/extensions/ |
D | libxt_ipvs.t | 15 -m ipvs --vmethod GATE;=;OK 20 -m ipvs --vproto 6 --vaddr 1.2.3.4/16 --vport 22 --vdir ORIGINAL --vmethod GATE;=;OK
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/external/u-boot/arch/arm/include/asm/arch-sunxi/ |
D | ccu.h | 33 #define GATE(_off, _bit) { \ macro
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/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/ |
D | confusables.txt | 9322 2FA8 ; 9580 ; MA #* ( ⾨ → 門 ) KANGXI RADICAL GATE → CJK UNIFIED IDEOGRAPH-9580 # 9334 2ED4 ; 95E8 ; MA #* ( ⻔ → 门 ) CJK RADICAL C-SIMPLIFIED GATE → CJK UNIFIED IDEOGRAPH-95E8 #
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D | UnicodeData.txt | 10881 2ED4;CJK RADICAL C-SIMPLIFIED GATE;So;0;ON;;;;;N;;;;; 11081 2FA8;KANGXI RADICAL GATE;So;0;ON;<compat> 9580;;;;N;;;;;
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/external/icu/icu4c/source/data/unidata/ |
D | confusables.txt | 9322 2FA8 ; 9580 ; MA #* ( ⾨ → 門 ) KANGXI RADICAL GATE → CJK UNIFIED IDEOGRAPH-9580 # 9334 2ED4 ; 95E8 ; MA #* ( ⻔ → 门 ) CJK RADICAL C-SIMPLIFIED GATE → CJK UNIFIED IDEOGRAPH-95E8 #
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/external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/ |
D | confusables.txt | 9322 2FA8 ; 9580 ; MA #* ( ⾨ → 門 ) KANGXI RADICAL GATE → CJK UNIFIED IDEOGRAPH-9580 # 9334 2ED4 ; 95E8 ; MA #* ( ⻔ → 门 ) CJK RADICAL C-SIMPLIFIED GATE → CJK UNIFIED IDEOGRAPH-95E8 #
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D | UnicodeData.txt | 10881 2ED4;CJK RADICAL C-SIMPLIFIED GATE;So;0;ON;;;;;N;;;;; 11081 2FA8;KANGXI RADICAL GATE;So;0;ON;<compat> 9580;;;;N;;;;;
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/external/icu/icu4c/source/data/unidata/norm2/ |
D | uts46.txt | 3225 2FA8 >9580 # 3.0 KANGXI RADICAL GATE
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/external/cldr/common/uca/ |
D | allkeys_DUCET.txt | 24799 2FA8 ; [.FB41.0020.0004.2FA8][.9580.0000.0000.2FA8] # KANGXI RADICAL GATE 24803 2ED4 ; [.FB41.0020.0004.2ED4][.95E8.0000.0000.2ED4] # CJK RADICAL C-SIMPLIFIED GATE
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D | allkeys_CLDR.txt | 32745 2FA8 ; [.FB41.0020.0004][.9580.0000.0000] # KANGXI RADICAL GATE 32749 2ED4 ; [.FB41.0020.0004][.95E8.0000.0000] # CJK RADICAL C-SIMPLIFIED GATE
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D | UCA_Rules.txt | 30364 <<< ⾨ # 3.0 [Hani/So] [FB41.0020.0004] [9580.0000.0000] U+2FA8 KANGXI RADICAL GATE 30366 <<< ⻔ # 3.0 [So] [FB41.0020.0004] [95E8.0000.0000] U+2ED4 CJK RADICAL C-SIMPLIFIED GATE
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/external/cldr/tools/java/org/unicode/cldr/draft/ |
D | Categories.txt | 10410 2ED4 So Ideograph Radical CJK CJK RADICAL C-SIMPLIFIED GATE 10610 2FA8 So Ideograph Radical CJK Kangxi KANGXI RADICAL GATE
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