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Searched refs:GFX10 (Results 1 – 25 of 84) sorted by relevance

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/external/mesa3d/src/amd/compiler/tests/
Dtest_assembler.cpp29 for (unsigned i = GFX6; i <= GFX10; i++) {
44 if (!setup_cs(NULL, (chip_class)GFX10))
63 if (!setup_cs(NULL, (chip_class)GFX10))
93 if (!setup_cs(NULL, (chip_class)GFX10))
126 if (!setup_cs(NULL, (chip_class)GFX10))
154 if (!setup_cs(NULL, (chip_class)GFX10))
183 if (!setup_cs(NULL, (chip_class)GFX10))
208 if (!setup_cs(NULL, (chip_class)GFX10))
232 for (unsigned i = GFX9; i <= GFX10; i++) {
250 for (unsigned i = GFX9; i <= GFX10; i++) {
Dtest_optimizer.cpp29 for (unsigned i = GFX9; i <= GFX10; i++) {
90 for (unsigned i = GFX9; i <= GFX10; i++) {
262 for (unsigned i = GFX8; i <= GFX10; i++) {
/external/mesa3d/src/amd/vulkan/winsys/null/
Dradv_null_winsys.c89 info->chip_class = GFX10; in radv_null_winsys_query_info()
112 else if (info->chip_class >= GFX10) in radv_null_winsys_query_info()
119 if (info->chip_class >= GFX10) in radv_null_winsys_query_info()
126 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256; in radv_null_winsys_query_info()
127 info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4; in radv_null_winsys_query_info()
128 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024; in radv_null_winsys_query_info()
/external/mesa3d/src/amd/compiler/
Daco_print_asm.cpp101 (chip >= GFX10 && (binary[pos] & 0xffff8000) == 0xd7610000)) { in disasm_instr()
109 if (chip >= GFX10 && l == 8 && in disasm_instr()
120 (chip >= GFX10 && (binary[pos] & 0xffff8000) == 0xd7038000) || /* v_add_u16_e64 + clamp */ in disasm_instr()
122 (chip >= GFX10 && (binary[pos] & 0xffff8000) == 0xd76d8000) || /* v_add3_u32 + clamp */ in disasm_instr()
125 bool has_literal = chip >= GFX10 && in disasm_instr()
128 } else if (chip >= GFX10 && l == 4 && ((binary[pos] & 0xfe0001ff) == 0x020000f9)) { in disasm_instr()
177 if (program->chip_class >= GFX10 && program->wave_size == 64) { in print_asm()
Daco_assembler.cpp26 else if (chip_class >= GFX10) in asm_context()
115 assert(ctx.chip_class >= GFX10); in emit_instruction()
119 assert(ctx.chip_class >= GFX10); in emit_instruction()
229 uint32_t soffset = ctx.chip_class >= GFX10 in emit_instruction()
296 } else if (ctx.chip_class >= GFX10) { in emit_instruction()
374 } else if (ctx.chip_class >= GFX10) { in emit_instruction()
380 if (ctx.chip_class <= GFX7 || ctx.chip_class >= GFX10) { in emit_instruction()
398 assert(!mtbuf->dlc || ctx.chip_class >= GFX10); in emit_instruction()
423 if (ctx.chip_class >= GFX10) { in emit_instruction()
463 if (ctx.chip_class >= GFX10) { in emit_instruction()
[all …]
Daco_insert_waitcnt.cpp147 if (chip >= GFX10) in wait_imm()
156 case GFX10: in pack()
175 if (chip < GFX10 && lgkm == wait_imm::unset_counter) in pack()
294 max_lgkm_cnt(program_->chip_class >= GFX10 ? 62 : 14), in wait_ctx()
295 max_vs_cnt(program_->chip_class >= GFX10 ? 62 : 0), in wait_ctx()
296 unordered_events(event_smem | (program_->chip_class < GFX10 ? event_flat : 0)), in wait_ctx()
467 if (ctx.chip_class < GFX10 && sync.scope <= scope_workgroup) in perform_barrier()
487 if (ctx.chip_class >= GFX10) { in force_waitcnt()
518 if (ctx.chip_class >= GFX10 && instr->format == Format::SMEM) { in kill()
681 assert(ctx.chip_class < GFX10); in update_counters_for_flat_load()
[all …]
Daco_live_var_analysis.cpp269 if (program->chip_class >= GFX10) { in get_extra_sgprs()
329 bool wgp = program->chip_class >= GFX10; /* assume WGP is used on Navi */ in calc_min_waves()
343 bool wgp = program->chip_class >= GFX10; /* assume WGP is used on Navi */ in update_vgpr_sgpr_demand()
363 if (waves_per_workgroup > 1 && program->chip_class < GFX10) in update_vgpr_sgpr_demand()
Daco_reduce_assign.cpp127 if (program->chip_class >= GFX10 && cluster_size == 64) in setup_reduce_temp()
129 if (program->chip_class >= GFX10 && gfx10_need_vtmp) in setup_reduce_temp()
Daco_lower_to_hw_instr.cpp83 if (chip >= GFX10) { in get_reduce_opcode()
93 if (chip >= GFX10) { in get_reduce_opcode()
105 if (chip >= GFX10) { in get_reduce_opcode()
115 if (chip >= GFX10) { in get_reduce_opcode()
125 if (chip >= GFX10) { in get_reduce_opcode()
135 if (chip >= GFX10) { in get_reduce_opcode()
213 if (ctx->program->chip_class >= GFX10) { in emit_int64_dpp_op()
334 if (ctx->program->chip_class >= GFX10) { in emit_int64_op()
504 …dentity[i].isLiteral() && op == aco_opcode::p_exclusive_scan && ctx->program->chip_class < GFX10) { in emit_reduction()
545 if (ctx->program->chip_class >= GFX10 && in emit_reduction()
[all …]
DREADME-ISA.md153 ## RDNA / GFX10 hazards
160 This is not mentioned by LLVM among the other GFX10 bugs, but LLVM doesn't use
195 ACO doesn't use FLAT load/store on GFX10, so is unaffected.
202 ACO doesn't use FLAT load/store on GFX10, so is unaffected.
DREADME.md146 However, GS store their output in VRAM (except GFX10/NGG).
153 On GFX10/NGG this limitation no longer exists, as the HW NGG GS can now export directly where it ne…
157 The merged stages on GFX9 (and GFX10/legacy) are: LSHS and ESGS. On GFX10/NGG the ESGS is merged wi…
183 ##### GFX9+ (including GFX10/legacy):
196 ##### NGG (GFX10+ only):
201 | GFX10/NGG HW stages: | LSHS | NGG GS | PS | ACO terminology |
/external/mesa3d/src/amd/vulkan/
Dradv_sqtt.c84 if (device->physical_device->rad_info.chip_class == GFX10) { in radv_emit_thread_trace_start()
239 case GFX10: in radv_copy_thread_trace_info_regs()
297 if (device->physical_device->rad_info.chip_class == GFX10) { in radv_emit_thread_trace_stop()
356 if (device->physical_device->rad_info.chip_class >= GFX10) in radv_emit_thread_trace_userdata()
377 if (device->physical_device->rad_info.chip_class == GFX10) in radv_emit_spi_config_cntl()
573 if (device->physical_device->rad_info.chip_class == GFX10) { in radv_is_thread_trace_complete()
591 if (device->physical_device->rad_info.chip_class == GFX10) { in radv_get_expected_buffer_size()
Dradv_shader.c884 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0) in radv_postprocess_config()
885 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0)); in radv_postprocess_config()
918 if (pdevice->rad_info.chip_class >= GFX10) { in radv_postprocess_config()
928 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
941 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
953 if (pdevice->rad_info.chip_class >= GFX10) { in radv_postprocess_config()
966 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | in radv_postprocess_config()
967 S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
972 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
989 if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) { in radv_postprocess_config()
[all …]
Dsi_cmd_buffer.c115 device->physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0); in si_emit_compute()
118 if (device->physical_device->rad_info.chip_class >= GFX10) { in si_emit_compute()
267 if (physical_device->rad_info.chip_class >= GFX10) { in si_emit_graphics()
303 if (physical_device->rad_info.chip_class >= GFX10) { in si_emit_graphics()
339 if (physical_device->rad_info.chip_class >= GFX10) { in si_emit_graphics()
367 if (physical_device->rad_info.chip_class == GFX10) in si_emit_graphics()
401 if (physical_device->rad_info.chip_class >= GFX10) { in si_emit_graphics()
411 if (physical_device->rad_info.chip_class >= GFX10) { in si_emit_graphics()
486 if (physical_device->rad_info.chip_class == GFX10) { in si_emit_graphics()
1254 if (chip_class >= GFX10) { in si_cs_emit_cache_flush()
[all …]
Dradv_rgp.c296 case GFX10: in radv_chip_class_to_sqtt_gfxip_level()
334 bool has_wave32 = rad_info->chip_class >= GFX10; in radv_fill_sqtt_asic_info()
531 case GFX10: in radv_chip_class_to_sqtt_version()
/external/mesa3d/src/amd/common/
Dac_gpu_info.c454 info->chip_class = GFX10; in ac_query_gpu_info()
558 if (info->chip_class >= GFX10) { in ac_query_gpu_info()
585 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024; in ac_query_gpu_info()
620 info->chip_class >= GFX10 || (info->chip_class >= GFX8 && info->max_se >= 2); in ac_query_gpu_info()
623 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10; in ac_query_gpu_info()
681 unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1; in ac_query_gpu_info()
774 if (info->chip_class >= GFX10) { in ac_query_gpu_info()
782 if (info->chip_class >= GFX10) in ac_query_gpu_info()
787 else if (info->chip_class == GFX10) in ac_query_gpu_info()
794 if (info->chip_class >= GFX10) { in ac_query_gpu_info()
[all …]
Dac_shadowed_regs.c836 else if (chip_class == GFX10) in ac_get_reg_ranges()
844 else if (chip_class == GFX10) in ac_get_reg_ranges()
850 if (chip_class == GFX10_3 || chip_class == GFX10) in ac_get_reg_ranges()
858 if (chip_class == GFX10_3 || chip_class == GFX10) in ac_get_reg_ranges()
868 else if (chip_class == GFX10) in ac_get_reg_ranges()
2940 } else if (info->chip_class == GFX10) { in ac_emulate_clear_state()
Damd_family.h127 GFX10, enumerator
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_binning.c409 if (sctx->chip_class >= GFX10) { in si_emit_dpbb_disable()
440 sctx->chip_class >= GFX10 ? R_028038_DB_DFSM_CONTROL : R_028060_DB_DFSM_CONTROL; in si_emit_dpbb_disable()
485 if (sctx->chip_class >= GFX10) { in si_emit_dpbb_state()
545 sctx->chip_class >= GFX10 ? R_028038_DB_DFSM_CONTROL : R_028060_DB_DFSM_CONTROL; in si_emit_dpbb_state()
Dsi_state_shaders.c405 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.chip_class >= GFX10) in polaris_set_vgt_vertex_reuse()
472 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid) in si_get_vs_vgpr_comp_cnt()
518 if (sscreen->info.chip_class >= GFX10) { in si_shader_hs()
531 if (sscreen->info.chip_class >= GFX10) in si_shader_hs()
548 S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) | in si_shader_hs()
549 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) | in si_shader_hs()
860 if (sscreen->info.chip_class >= GFX10) { in si_shader_gs()
869 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) | in si_shader_gs()
870 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) | in si_shader_gs()
879 if (sscreen->info.chip_class >= GFX10) { in si_shader_gs()
[all …]
Dsi_cp_reg_shadowing.c73 if (sctx->chip_class == GFX10) { in si_create_shadowing_ib_preamble()
92 if (sctx->chip_class >= GFX10) { in si_create_shadowing_ib_preamble()
Dsi_pipe.c149 sscreen->info.chip_class <= GFX10 ? AC_TM_FORCE_ENABLE_XNACK : 0) | in si_init_compiler()
186 if (sctx->chip_class >= GFX10 && sctx->has_graphics) in si_destroy_context()
553 if (sctx->chip_class >= GFX10) in si_create_context()
580 if (sctx->chip_class >= GFX10) in si_create_context()
991 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) { in radeonsi_screen_create_impl()
1133 if (sscreen->info.chip_class >= GFX10) in radeonsi_screen_create_impl()
1190 sscreen->info.chip_class >= GFX10 && in radeonsi_screen_create_impl()
1198 if (sscreen->info.chip_class >= GFX10) { in radeonsi_screen_create_impl()
1294 if (sscreen->info.chip_class >= GFX10) { in radeonsi_screen_create_impl()
Dsi_compute.c195 S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) | in si_create_compute_state_async()
196 S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) | in si_create_compute_state_async()
199 if (sscreen->info.chip_class < GFX10) { in si_create_compute_state_async()
396 sctx->chip_class >= GFX10 ? 0x20 : 0); in si_emit_initial_compute_regs()
399 if (sctx->chip_class >= GFX10) { in si_emit_initial_compute_regs()
734 if (sctx->chip_class >= GFX10 && waves_per_threadgroup == 1) in si_emit_dispatch_packets()
Dsi_state.c581 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10) in si_create_blend_state_mode()
592 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10 && logicop_enable) in si_create_blend_state_mode()
758 if (sctx->chip_class >= GFX10) { in si_emit_clip_regs()
930 … S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.chip_class >= GFX10 ? rs->polygon_mode_enabled : 0)); in si_create_rs_state()
1363 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect; in si_emit_db_render_state()
1932 if (sscreen->info.chip_class >= GFX10) { in si_is_sampler_format_supported()
2089 if (sscreen->info.chip_class >= GFX10) { in si_is_vertex_format_supported()
2309 if (sctx->chip_class >= GFX10) { in si_initialize_color_surface()
2358 if (sctx->chip_class >= GFX10) { in si_initialize_color_surface()
2405 if (sctx->chip_class >= GFX10) { in si_init_depth_surface()
[all …]
/external/mesa3d/docs/relnotes/
D19.3.2.rst50 - [GFX10] Glitch rendering Custom Avatars in Beat Saber
127 - radv: return the correct pitch for linear mipmaps on GFX10

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