Searched refs:GICC_CTLR (Results 1 – 19 of 19) sorted by relevance
| /external/arm-trusted-firmware/drivers/arm/gic/v2/ |
| D | gicv2_private.h | 62 return mmio_read_32(base + GICC_CTLR); in gicc_read_ctlr()
116 mmio_write_32(base + GICC_CTLR, val); in gicc_write_ctlr()
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| /external/arm-trusted-firmware/plat/nvidia/tegra/include/ |
| D | plat_macros.S | 37 ldr w10, [x16, #GICC_CTLR]
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| /external/arm-trusted-firmware/plat/amlogic/common/include/ |
| D | plat_macros.S | 41 ldr w10, [x17, #GICC_CTLR]
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| /external/arm-trusted-firmware/plat/hisilicon/hikey/include/ |
| D | plat_macros.S | 44 ldr w10, [x17, #GICC_CTLR]
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/include/ |
| D | plat_macros.S | 42 ldr w10, [x27, #GICC_CTLR]
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| /external/arm-trusted-firmware/plat/renesas/rcar/include/ |
| D | plat_macros.S | 39 ldr w10, [x17, #GICC_CTLR]
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| /external/arm-trusted-firmware/plat/mediatek/mt6795/include/ |
| D | plat_macros.S | 36 ldr w10, [x17, #GICC_CTLR]
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| /external/arm-trusted-firmware/plat/hisilicon/hikey960/include/ |
| D | plat_macros.S | 44 ldr w10, [x17, #GICC_CTLR]
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| /external/arm-trusted-firmware/plat/mediatek/mt8173/include/ |
| D | plat_macros.S | 42 ldr w10, [x17, #GICC_CTLR]
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| /external/u-boot/arch/arm/include/asm/ |
| D | gic.h | 38 #define GICC_CTLR 0x0000 macro
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| /external/arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/ |
| D | zynqmp_helpers.S | 38 str w0, [x1, #GICC_CTLR]
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| /external/arm-trusted-firmware/include/plat/arm/common/aarch64/ |
| D | arm_macros.S | 69 ldr w10, [x17, #GICC_CTLR]
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| /external/arm-trusted-firmware/plat/xilinx/versal/include/ |
| D | plat_macros.S | 69 ldr w10, [x17, #GICC_CTLR]
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| /external/arm-trusted-firmware/include/plat/marvell/common/aarch64/ |
| D | marvell_macros.S | 78 ldr w10, [x17, #GICC_CTLR]
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| /external/arm-trusted-firmware/plat/rockchip/common/include/ |
| D | plat_macros.S | 77 ldr w10, [x27, #GICC_CTLR]
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| /external/arm-trusted-firmware/include/drivers/arm/ |
| D | gicv2.h | 58 #define GICC_CTLR U(0x0) macro
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| /external/u-boot/arch/arm/lib/ |
| D | gic_64.S | 153 str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
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| /external/u-boot/arch/arm/cpu/armv7/sunxi/ |
| D | psci.c | 312 setbits_le32(GICC_BASE + GICC_CTLR, BIT(3)); in psci_arch_init()
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| /external/u-boot/arch/arm/cpu/armv7/ |
| D | nonsec_virt.S | 176 str r1, [r3, #GICC_CTLR] @ and clear all other bits
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