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Searched refs:GPIO1 (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/board/technexion/tao3530/
Dtao3530.c135 writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); in misc_init_r()
140 writel(GPIO10 | GPIO8 | GPIO2 | GPIO1, in misc_init_r()
/external/u-boot/board/Arcturus/ucp1020/
Ducp1020.h12 #define GPIO1 30 macro
/external/u-boot/board/ti/beagle/
Dbeagle.c488 writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1, in misc_init_r()
494 writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); in misc_init_r()
/external/u-boot/arch/arm/dts/
Dbcm2835-rpi-cm1-io1.dts21 "GPIO1",
Dbcm2837-rpi-cm3-io3.dts21 "GPIO1",
Daxp81x.dtsi67 pins = "GPIO1";
Dfsl-imx8qm-apalis.dts44 /* Apalis GPIO1 */
/external/u-boot/arch/arm/include/asm/arch-omap3/
Domap.h110 #define GPIO1 (0x1 << 1) macro
/external/u-boot/doc/imx/common/
Dimx5.txt21 connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
/external/arm-trusted-firmware/plat/intel/soc/common/soc/
Dsocfpga_system_manager.c53 mmio_write_32(SOCFPGA_L4_PER_SCR(GPIO1), DISABLE_L4_FIREWALL); in enable_ns_peripheral_access()
Dsocfpga_reset_manager.c35 RSTMGR_FIELD(PER1, GPIO1)); in deassert_peripheral_reset()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/gpio/
Dmtgpio.h24 GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, enumerator
/external/u-boot/doc/device-tree-bindings/pinctrl/
Dmarvell,armada-37xx-pinctrl.txt40 - pin 11 (GPIO1-11)
/external/u-boot/arch/arm/include/asm/arch-pxa/
Dpxa-regs.h1317 #define GPIO1 0x40e10128 macro
1509 #define GPIO1 0x40e100b8 macro