Searched refs:HHI_MPLL_CNTL7 (Results 1 – 5 of 5) sorted by relevance
| /external/u-boot/arch/arm/include/asm/arch-meson/ |
| D | clock-axg.h | 85 #define HHI_MPLL_CNTL7 0x298 macro
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| D | clock-g12a.h | 83 #define HHI_MPLL_CNTL7 0x294 macro
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| D | clock-gx.h | 80 #define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */ macro
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| /external/u-boot/drivers/clk/meson/ |
| D | axg.c | 130 {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
131 {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
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| D | gxbb.c | 178 MESON_GATE(CLKID_MPLL0, HHI_MPLL_CNTL7, 14),
618 {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
619 {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
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