Searched refs:HHI_MPLL_CNTL9 (Results 1 – 4 of 4) sorted by relevance
| /external/u-boot/drivers/clk/meson/ |
| D | axg.c | 43 MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
140 {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
141 {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
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| D | gxbb.c | 180 MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
628 {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
629 {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
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| /external/u-boot/arch/arm/include/asm/arch-meson/ |
| D | clock-axg.h | 87 #define HHI_MPLL_CNTL9 0x2A0 macro
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| D | clock-gx.h | 82 #define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */ macro
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