Home
last modified time | relevance | path

Searched refs:HHI_PCIE_PLL_CNTL1 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-meson/
Dclock-axg.h40 #define HHI_PCIE_PLL_CNTL1 0xdC macro
Dclock-g12a.h32 #define HHI_PCIE_PLL_CNTL1 0x09C macro
/external/u-boot/drivers/clk/meson/
Dg12a.c864 regmap_write(priv->map, HHI_PCIE_PLL_CNTL1, 0x00000000); in meson_pcie_pll_set_rate()