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Searched refs:HHI_PCIE_PLL_CNTL3 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-meson/
Dclock-axg.h42 #define HHI_PCIE_PLL_CNTL3 0xe4 macro
Dclock-g12a.h34 #define HHI_PCIE_PLL_CNTL3 0x0A4 macro
/external/u-boot/drivers/clk/meson/
Dg12a.c866 regmap_write(priv->map, HHI_PCIE_PLL_CNTL3, 0x10058e00); in meson_pcie_pll_set_rate()