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Searched refs:HHI_VIID_CLK_DIV (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-meson/
Dclock-axg.h50 #define HHI_VIID_CLK_DIV 0x128 macro
Dclock-g12a.h45 #define HHI_VIID_CLK_DIV 0x128 macro
Dclock-gx.h32 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ macro
/external/u-boot/drivers/video/meson/
Dmeson_vclk.c28 #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ macro
270 hhi_update_bits(HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
288 hhi_update_bits(HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
292 hhi_update_bits(HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()