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Searched refs:HREG (Results 1 – 5 of 5) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Df16-convert.ll5 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0]
6 ; CHECK-NEXT: fcvt s0, [[HREG]]
16 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0]
17 ; CHECK-NEXT: fcvt d0, [[HREG]]
27 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, w1, sxtw #1]
28 ; CHECK-NEXT: fcvt s0, [[HREG]]
40 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, w1, sxtw #1]
41 ; CHECK-NEXT: fcvt d0, [[HREG]]
53 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, x1, lsl #1]
54 ; CHECK-NEXT: fcvt s0, [[HREG]]
[all …]
Darm64-xaluo.ll210 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
211 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
379 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
380 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
575 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
576 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Df16-convert.ll5 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0]
6 ; CHECK-NEXT: fcvt s0, [[HREG]]
16 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0]
17 ; CHECK-NEXT: fcvt d0, [[HREG]]
27 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, w1, sxtw #1]
28 ; CHECK-NEXT: fcvt s0, [[HREG]]
40 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, w1, sxtw #1]
41 ; CHECK-NEXT: fcvt d0, [[HREG]]
53 ; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, x1, lsl #1]
54 ; CHECK-NEXT: fcvt s0, [[HREG]]
[all …]
Darm64-xaluo.ll210 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
211 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
480 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
481 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
493 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
494 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
713 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
714 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
/external/vixl/src/aarch64/
Doperands-aarch64.cc166 #define HREG(n) h##n, macro
167 const VRegister VRegister::hregisters[] = {AARCH64_REGISTER_CODE_LIST(HREG)};
168 #undef HREG