1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
4 * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <dm/device.h>
10 #include <generic-phy.h>
11 #include <asm/io.h>
12 #include <asm/arch/sys_proto.h>
13 #include <syscon.h>
14 #include <regmap.h>
15
16 /* PLLCTRL Registers */
17 #define PLL_STATUS 0x00000004
18 #define PLL_GO 0x00000008
19 #define PLL_CONFIGURATION1 0x0000000C
20 #define PLL_CONFIGURATION2 0x00000010
21 #define PLL_CONFIGURATION3 0x00000014
22 #define PLL_CONFIGURATION4 0x00000020
23
24 #define PLL_REGM_MASK 0x001FFE00
25 #define PLL_REGM_SHIFT 9
26 #define PLL_REGM_F_MASK 0x0003FFFF
27 #define PLL_REGM_F_SHIFT 0
28 #define PLL_REGN_MASK 0x000001FE
29 #define PLL_REGN_SHIFT 1
30 #define PLL_SELFREQDCO_MASK 0x0000000E
31 #define PLL_SELFREQDCO_SHIFT 1
32 #define PLL_SD_MASK 0x0003FC00
33 #define PLL_SD_SHIFT 10
34 #define SET_PLL_GO 0x1
35 #define PLL_TICOPWDN BIT(16)
36 #define PLL_LDOPWDN BIT(15)
37 #define PLL_LOCK 0x2
38 #define PLL_IDLE 0x1
39
40 /* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/
41 #define SATA_PLL_SOFT_RESET (1<<18)
42
43 /* PHY POWER CONTROL Register */
44 #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
45 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
46
47 #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
48 #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
49
50 #define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
51 #define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
52
53 /* PHY RX Registers */
54 #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
55 #define INTERFACE_MASK GENMASK(31, 27)
56 #define INTERFACE_SHIFT 27
57 #define INTERFACE_MODE_USBSS BIT(4)
58 #define INTERFACE_MODE_SATA_1P5 BIT(3)
59 #define INTERFACE_MODE_SATA_3P0 BIT(2)
60 #define INTERFACE_MODE_PCIE BIT(0)
61
62 #define LOSD_MASK GENMASK(17, 14)
63 #define LOSD_SHIFT 14
64 #define MEM_PLLDIV GENMASK(6, 5)
65
66 #define PIPE3_PHY_RX_TRIM 0x0000001C
67 #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
68 #define MEM_DLL_TRIM_SHIFT 30
69
70 #define PIPE3_PHY_RX_DLL 0x00000024
71 #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
72 #define MEM_DLL_PHINT_RATE_SHIFT 30
73
74 #define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
75 #define MEM_HS_RATE_MASK GENMASK(28, 27)
76 #define MEM_HS_RATE_SHIFT 27
77 #define MEM_OVRD_HS_RATE BIT(26)
78 #define MEM_OVRD_HS_RATE_SHIFT 26
79 #define MEM_CDR_FASTLOCK BIT(23)
80 #define MEM_CDR_FASTLOCK_SHIFT 23
81 #define MEM_CDR_LBW_MASK GENMASK(22, 21)
82 #define MEM_CDR_LBW_SHIFT 21
83 #define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
84 #define MEM_CDR_STEPCNT_SHIFT 19
85 #define MEM_CDR_STL_MASK GENMASK(18, 16)
86 #define MEM_CDR_STL_SHIFT 16
87 #define MEM_CDR_THR_MASK GENMASK(15, 13)
88 #define MEM_CDR_THR_SHIFT 13
89 #define MEM_CDR_THR_MODE BIT(12)
90 #define MEM_CDR_THR_MODE_SHIFT 12
91 #define MEM_CDR_2NDO_SDM_MODE BIT(11)
92 #define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
93
94 #define PIPE3_PHY_RX_EQUALIZER 0x00000038
95 #define MEM_EQLEV_MASK GENMASK(31, 16)
96 #define MEM_EQLEV_SHIFT 16
97 #define MEM_EQFTC_MASK GENMASK(15, 11)
98 #define MEM_EQFTC_SHIFT 11
99 #define MEM_EQCTL_MASK GENMASK(10, 7)
100 #define MEM_EQCTL_SHIFT 7
101 #define MEM_OVRD_EQLEV BIT(2)
102 #define MEM_OVRD_EQLEV_SHIFT 2
103 #define MEM_OVRD_EQFTC BIT(1)
104 #define MEM_OVRD_EQFTC_SHIFT 1
105
106 #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
107 #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
108 #define MEM_CDR_LOS_SOURCE_SHIFT 9
109
110 #define PLL_IDLE_TIME 100 /* in milliseconds */
111 #define PLL_LOCK_TIME 100 /* in milliseconds */
112
113 enum pipe3_mode { PIPE3_MODE_PCIE = 1,
114 PIPE3_MODE_SATA,
115 PIPE3_MODE_USBSS };
116
117 struct pipe3_settings {
118 u8 ana_interface;
119 u8 ana_losd;
120 u8 dig_fastlock;
121 u8 dig_lbw;
122 u8 dig_stepcnt;
123 u8 dig_stl;
124 u8 dig_thr;
125 u8 dig_thr_mode;
126 u8 dig_2ndo_sdm_mode;
127 u8 dig_hs_rate;
128 u8 dig_ovrd_hs_rate;
129 u8 dll_trim_sel;
130 u8 dll_phint_rate;
131 u8 eq_lev;
132 u8 eq_ftc;
133 u8 eq_ctl;
134 u8 eq_ovrd_lev;
135 u8 eq_ovrd_ftc;
136 };
137
138 struct omap_pipe3 {
139 void __iomem *pll_ctrl_base;
140 void __iomem *phy_rx;
141 void __iomem *power_reg;
142 void __iomem *pll_reset_reg;
143 struct pipe3_dpll_map *dpll_map;
144 enum pipe3_mode mode;
145 struct pipe3_settings settings;
146 };
147
148 struct pipe3_dpll_params {
149 u16 m;
150 u8 n;
151 u8 freq:3;
152 u8 sd;
153 u32 mf;
154 };
155
156 struct pipe3_dpll_map {
157 unsigned long rate;
158 struct pipe3_dpll_params params;
159 };
160
161 struct pipe3_data {
162 enum pipe3_mode mode;
163 struct pipe3_dpll_map *dpll_map;
164 struct pipe3_settings settings;
165 };
166
omap_pipe3_readl(void __iomem * addr,unsigned offset)167 static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
168 {
169 return readl(addr + offset);
170 }
171
omap_pipe3_writel(void __iomem * addr,unsigned offset,u32 data)172 static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
173 u32 data)
174 {
175 writel(data, addr + offset);
176 }
177
omap_pipe3_get_dpll_params(struct omap_pipe3 * pipe3)178 static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
179 *pipe3)
180 {
181 u32 rate;
182 struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
183
184 rate = get_sys_clk_freq();
185
186 for (; dpll_map->rate; dpll_map++) {
187 if (rate == dpll_map->rate)
188 return &dpll_map->params;
189 }
190
191 printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
192 __func__, rate);
193 return NULL;
194 }
195
omap_pipe3_wait_lock(struct omap_pipe3 * pipe3)196 static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
197 {
198 u32 val;
199 int timeout = PLL_LOCK_TIME;
200
201 do {
202 mdelay(1);
203 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
204 if (val & PLL_LOCK)
205 break;
206 } while (--timeout);
207
208 if (!(val & PLL_LOCK)) {
209 printf("%s: DPLL failed to lock\n", __func__);
210 return -EBUSY;
211 }
212
213 return 0;
214 }
215
omap_pipe3_dpll_program(struct omap_pipe3 * pipe3)216 static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
217 {
218 u32 val;
219 struct pipe3_dpll_params *dpll_params;
220
221 dpll_params = omap_pipe3_get_dpll_params(pipe3);
222 if (!dpll_params) {
223 printf("%s: Invalid DPLL parameters\n", __func__);
224 return -EINVAL;
225 }
226
227 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
228 val &= ~PLL_REGN_MASK;
229 val |= dpll_params->n << PLL_REGN_SHIFT;
230 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
231
232 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
233 val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
234 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
235 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
236
237 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
238 val &= ~PLL_REGM_MASK;
239 val |= dpll_params->m << PLL_REGM_SHIFT;
240 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
241
242 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
243 val &= ~PLL_REGM_F_MASK;
244 val |= dpll_params->mf << PLL_REGM_F_SHIFT;
245 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
246
247 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
248 val &= ~PLL_SD_MASK;
249 val |= dpll_params->sd << PLL_SD_SHIFT;
250 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
251
252 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
253
254 return omap_pipe3_wait_lock(pipe3);
255 }
256
omap_control_pipe3_power(struct omap_pipe3 * pipe3,int on)257 static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
258 {
259 u32 val, rate;
260
261 val = readl(pipe3->power_reg);
262
263 rate = get_sys_clk_freq();
264 rate = rate/1000000;
265
266 if (on) {
267 val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
268 PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
269 val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
270 writel(val, pipe3->power_reg);
271
272 /* Power up TX before RX for SATA & USB */
273 val |= PIPE3_PHY_TX_POWERON;
274 writel(val, pipe3->power_reg);
275
276 val |= PIPE3_PHY_RX_POWERON;
277 writel(val, pipe3->power_reg);
278 } else {
279 val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
280 writel(val, pipe3->power_reg);
281 }
282 }
283
ti_pipe3_calibrate(struct omap_pipe3 * phy)284 static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
285 {
286 u32 val;
287 struct pipe3_settings *s = &phy->settings;
288
289 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
290 val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
291 val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
292 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
293
294 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
295 val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
296 MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
297 MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
298 val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
299 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
300 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
301 s->dig_lbw << MEM_CDR_LBW_SHIFT |
302 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
303 s->dig_stl << MEM_CDR_STL_SHIFT |
304 s->dig_thr << MEM_CDR_THR_SHIFT |
305 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
306 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
307 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
308
309 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
310 val &= ~MEM_DLL_TRIM_SEL_MASK;
311 val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
312 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
313
314 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
315 val &= ~MEM_DLL_PHINT_RATE_MASK;
316 val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
317 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
318
319 val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
320 val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
321 MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
322 val |= s->eq_lev << MEM_EQLEV_SHIFT |
323 s->eq_ftc << MEM_EQFTC_SHIFT |
324 s->eq_ctl << MEM_EQCTL_SHIFT |
325 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
326 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
327 omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
328
329 if (phy->mode == PIPE3_MODE_SATA) {
330 val = omap_pipe3_readl(phy->phy_rx,
331 SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
332 val &= ~MEM_CDR_LOS_SOURCE_MASK;
333 omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
334 val);
335 }
336 }
337
pipe3_init(struct phy * phy)338 static int pipe3_init(struct phy *phy)
339 {
340 int ret;
341 u32 val;
342 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
343
344 /* Program the DPLL only if not locked */
345 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
346 if (!(val & PLL_LOCK)) {
347 ret = omap_pipe3_dpll_program(pipe3);
348 if (ret)
349 return ret;
350
351 ti_pipe3_calibrate(pipe3);
352 } else {
353 /* else just bring it out of IDLE mode */
354 val = omap_pipe3_readl(pipe3->pll_ctrl_base,
355 PLL_CONFIGURATION2);
356 if (val & PLL_IDLE) {
357 val &= ~PLL_IDLE;
358 omap_pipe3_writel(pipe3->pll_ctrl_base,
359 PLL_CONFIGURATION2, val);
360 ret = omap_pipe3_wait_lock(pipe3);
361 if (ret)
362 return ret;
363 }
364 }
365 return 0;
366 }
367
pipe3_power_on(struct phy * phy)368 static int pipe3_power_on(struct phy *phy)
369 {
370 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
371
372 /* Power up the PHY */
373 omap_control_pipe3_power(pipe3, 1);
374
375 return 0;
376 }
377
pipe3_power_off(struct phy * phy)378 static int pipe3_power_off(struct phy *phy)
379 {
380 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
381
382 /* Power down the PHY */
383 omap_control_pipe3_power(pipe3, 0);
384
385 return 0;
386 }
387
pipe3_exit(struct phy * phy)388 static int pipe3_exit(struct phy *phy)
389 {
390 u32 val;
391 int timeout = PLL_IDLE_TIME;
392 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
393
394 pipe3_power_off(phy);
395
396 /* Put DPLL in IDLE mode */
397 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
398 val |= PLL_IDLE;
399 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
400
401 /* wait for LDO and Oscillator to power down */
402 do {
403 mdelay(1);
404 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
405 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
406 break;
407 } while (--timeout);
408
409 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
410 pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
411 __func__, val);
412 return -EBUSY;
413 }
414
415 if (pipe3->pll_reset_reg) {
416 val = readl(pipe3->pll_reset_reg);
417 writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
418 mdelay(1);
419 writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
420 }
421
422 return 0;
423 }
424
get_reg(struct udevice * dev,const char * name)425 static void *get_reg(struct udevice *dev, const char *name)
426 {
427 struct udevice *syscon;
428 struct regmap *regmap;
429 const fdt32_t *cell;
430 int len, err;
431 void *base;
432
433 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
434 name, &syscon);
435 if (err) {
436 pr_err("unable to find syscon device for %s (%d)\n",
437 name, err);
438 return NULL;
439 }
440
441 regmap = syscon_get_regmap(syscon);
442 if (IS_ERR(regmap)) {
443 pr_err("unable to find regmap for %s (%ld)\n",
444 name, PTR_ERR(regmap));
445 return NULL;
446 }
447
448 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
449 &len);
450 if (len < 2*sizeof(fdt32_t)) {
451 pr_err("offset not available for %s\n", name);
452 return NULL;
453 }
454
455 base = regmap_get_range(regmap, 0);
456 if (!base)
457 return NULL;
458
459 return fdtdec_get_number(cell + 1, 1) + base;
460 }
461
pipe3_phy_probe(struct udevice * dev)462 static int pipe3_phy_probe(struct udevice *dev)
463 {
464 fdt_addr_t addr;
465 fdt_size_t sz;
466 struct omap_pipe3 *pipe3 = dev_get_priv(dev);
467 struct pipe3_data *data;
468
469 /* PHY_RX */
470 addr = devfdt_get_addr_size_index(dev, 0, &sz);
471 if (addr == FDT_ADDR_T_NONE) {
472 pr_err("missing phy_rx address\n");
473 return -EINVAL;
474 }
475
476 pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
477 if (!pipe3->phy_rx) {
478 pr_err("unable to remap phy_rx\n");
479 return -EINVAL;
480 }
481
482 /* PLLCTRL */
483 addr = devfdt_get_addr_size_index(dev, 2, &sz);
484 if (addr == FDT_ADDR_T_NONE) {
485 pr_err("missing pll ctrl address\n");
486 return -EINVAL;
487 }
488
489 pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
490 if (!pipe3->pll_ctrl_base) {
491 pr_err("unable to remap pll ctrl\n");
492 return -EINVAL;
493 }
494
495 pipe3->power_reg = get_reg(dev, "syscon-phy-power");
496 if (!pipe3->power_reg)
497 return -EINVAL;
498
499 data = (struct pipe3_data *)dev_get_driver_data(dev);
500 pipe3->mode = data->mode;
501 pipe3->dpll_map = data->dpll_map;
502 pipe3->settings = data->settings;
503
504 if (pipe3->mode == PIPE3_MODE_SATA) {
505 pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
506 if (!pipe3->pll_reset_reg)
507 return -EINVAL;
508 }
509
510 return 0;
511 }
512
513 static struct pipe3_dpll_map dpll_map_sata[] = {
514 {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
515 {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
516 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
517 {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
518 {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
519 {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
520 { }, /* Terminator */
521 };
522
523 static struct pipe3_dpll_map dpll_map_usb[] = {
524 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
525 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
526 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
527 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
528 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
529 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
530 { }, /* Terminator */
531 };
532
533 static struct pipe3_data data_usb = {
534 .mode = PIPE3_MODE_USBSS,
535 .dpll_map = dpll_map_usb,
536 .settings = {
537 /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
538 .ana_interface = INTERFACE_MODE_USBSS,
539 .ana_losd = 0xa,
540 .dig_fastlock = 1,
541 .dig_lbw = 3,
542 .dig_stepcnt = 0,
543 .dig_stl = 0x3,
544 .dig_thr = 1,
545 .dig_thr_mode = 1,
546 .dig_2ndo_sdm_mode = 0,
547 .dig_hs_rate = 0,
548 .dig_ovrd_hs_rate = 1,
549 .dll_trim_sel = 0x2,
550 .dll_phint_rate = 0x3,
551 .eq_lev = 0,
552 .eq_ftc = 0,
553 .eq_ctl = 0x9,
554 .eq_ovrd_lev = 0,
555 .eq_ovrd_ftc = 0,
556 },
557 };
558
559 static struct pipe3_data data_sata = {
560 .mode = PIPE3_MODE_SATA,
561 .dpll_map = dpll_map_sata,
562 .settings = {
563 /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
564 .ana_interface = INTERFACE_MODE_SATA_3P0,
565 .ana_losd = 0x5,
566 .dig_fastlock = 1,
567 .dig_lbw = 3,
568 .dig_stepcnt = 0,
569 .dig_stl = 0x3,
570 .dig_thr = 1,
571 .dig_thr_mode = 1,
572 .dig_2ndo_sdm_mode = 0,
573 .dig_hs_rate = 0, /* Not in TRM preferred settings */
574 .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
575 .dll_trim_sel = 0x1,
576 .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
577 .eq_lev = 0,
578 .eq_ftc = 0x1f,
579 .eq_ctl = 0,
580 .eq_ovrd_lev = 1,
581 .eq_ovrd_ftc = 1,
582 },
583 };
584
585 static const struct udevice_id pipe3_phy_ids[] = {
586 { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
587 { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
588 { }
589 };
590
591 static struct phy_ops pipe3_phy_ops = {
592 .init = pipe3_init,
593 .power_on = pipe3_power_on,
594 .power_off = pipe3_power_off,
595 .exit = pipe3_exit,
596 };
597
598 U_BOOT_DRIVER(pipe3_phy) = {
599 .name = "pipe3_phy",
600 .id = UCLASS_PHY,
601 .of_match = pipe3_phy_ids,
602 .ops = &pipe3_phy_ops,
603 .probe = pipe3_phy_probe,
604 .priv_auto_alloc_size = sizeof(struct omap_pipe3),
605 };
606