| /external/capstone/arch/XCore/ |
| D | XCoreDisassembler.c | 75 static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
78 static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
81 static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
84 static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
87 static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
90 static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
93 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn,
96 static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn,
99 static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn,
102 static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn,
[all …]
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| /external/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 46 uint64_t &Size, uint16_t &Insn) { in readInstruction16() argument
53 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
58 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
65 Insn = in readInstruction32()
93 unsigned Insn,
98 unsigned Insn,
103 unsigned Insn,
108 unsigned Insn,
113 unsigned Insn,
118 unsigned Insn,
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/Disassembler/ |
| D | XCoreDisassembler.cpp | 46 uint64_t &Size, uint16_t &Insn) { in readInstruction16() argument
53 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
58 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
65 Insn = in readInstruction32()
93 unsigned Insn,
98 unsigned Insn,
103 unsigned Insn,
108 unsigned Insn,
113 unsigned Insn,
118 unsigned Insn,
[all …]
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| /external/capstone/arch/ARM/ |
| D | ARMDisassembler.c | 172 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn,
174 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
177 unsigned Insn, uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn,
180 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn,
182 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn,
184 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn,
187 unsigned Insn, uint64_t Adddress, const void *Decoder);
188 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
190 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 192 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
194 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
197 unsigned Insn,
200 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
202 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
204 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
206 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
210 unsigned Insn,
213 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
215 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
[all …]
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
191 unsigned Insn,
194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
204 unsigned Insn,
207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
[all …]
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 102 unsigned Insn,
136 unsigned Insn,
206 unsigned Insn,
256 unsigned Insn,
261 unsigned Insn,
266 unsigned Insn,
271 unsigned Insn,
276 unsigned Insn,
281 unsigned Insn,
286 unsigned Insn,
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 53 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
56 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
59 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
62 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
69 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
75 uint32_t &Insn) { in readInstruction32() argument
83 Insn = in readInstruction32()
89 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
100 AluOp = (Insn >> 8) & 0x7; in PostOperandDecodeAdjust()
104 AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1); in PostOperandDecodeAdjust()
[all …]
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| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 53 static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn,
56 static DecodeStatus decodeRrMemoryValue(MCInst &Inst, unsigned Insn,
59 static DecodeStatus decodeSplsValue(MCInst &Inst, unsigned Insn,
62 static DecodeStatus decodeBranch(MCInst &Inst, unsigned Insn, uint64_t Address,
69 static DecodeStatus decodeShiftImm(MCInst &Inst, unsigned Insn,
75 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
83 Insn = in readInstruction32()
89 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
100 AluOp = (Insn >> 8) & 0x7; in PostOperandDecodeAdjust()
104 AluOp |= 0x20 | (((Insn >> 3) & 0xf) << 1); in PostOperandDecodeAdjust()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 112 unsigned Insn,
146 unsigned Insn,
216 unsigned Insn,
266 unsigned Insn,
271 unsigned Insn,
276 unsigned Insn,
281 unsigned Insn,
285 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
289 unsigned Insn,
294 unsigned Insn,
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/Disassembler/ |
| D | ARCDisassembler.cpp | 52 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
55 Insn = in readInstruction32()
61 uint64_t &Size, uint64_t &Insn) { in readInstruction64() argument
63 Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) | in readInstruction64()
71 uint64_t &Size, uint64_t &Insn) { in readInstruction48() argument
73 Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) | in readInstruction48()
80 uint64_t &Size, uint32_t &Insn) { in readInstruction16() argument
82 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
146 static unsigned decodeCField(unsigned Insn) { in decodeCField() argument
147 return fieldFromInstruction(Insn, 6, 6); in decodeCField()
[all …]
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| /external/capstone/arch/Mips/ |
| D | MipsDisassembler.c | 77 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
113 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
129 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
132 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
135 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
138 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
141 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
144 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
146 static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
149 static DecodeStatus DecodeCOP2Mem(MCInst *Inst, unsigned Insn,
[all …]
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| /external/llvm/utils/TableGen/ |
| D | PseudoLoweringEmitter.cpp | 56 CodeGenInstruction &Insn,
74 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, in addDagOperandMapping() argument
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) in addDagOperandMapping()
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); in addDagOperandMapping()
101 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) in addDagOperandMapping()
103 OpsAdded += Insn.Operands[i].MINumOperands; in addDagOperandMapping()
112 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); in addDagOperandMapping()
140 CodeGenInstruction Insn(Operator); in evaluateExpansion() local
142 if (Insn.isCodeGenOnly || Insn.isPseudo) in evaluateExpansion()
146 if (Insn.Operands.size() != Dag->getNumArgs()) in evaluateExpansion()
[all …]
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| D | FixedLenDecoderEmitter.cpp | 367 void insnWithID(insn_t &Insn, unsigned Opcode) const { in insnWithID() argument
380 Insn.push_back(BIT_UNSET); in insnWithID()
382 Insn.push_back(bitFromBits(Bits, i)); in insnWithID()
396 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit,
424 const insn_t &Insn) const;
504 insn_t Insn; in Filter() local
507 Owner->insnWithID(Insn, Owner->Opcodes[i]); in Filter()
511 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits); in Filter()
926 bool FilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn, in fieldFromInsn() argument
931 if (Insn[StartBit + i] == BIT_UNSET) in fieldFromInsn()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | PseudoLoweringEmitter.cpp | 56 CodeGenInstruction &Insn,
74 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn, in addDagOperandMapping() argument
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) in addDagOperandMapping()
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); in addDagOperandMapping()
101 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) in addDagOperandMapping()
103 OpsAdded += Insn.Operands[i].MINumOperands; in addDagOperandMapping()
112 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); in addDagOperandMapping()
140 CodeGenInstruction Insn(Operator); in evaluateExpansion() local
142 if (Insn.isCodeGenOnly || Insn.isPseudo) in evaluateExpansion()
146 if (Insn.Operands.size() != Dag->getNumArgs()) in evaluateExpansion()
[all …]
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| D | FixedLenDecoderEmitter.cpp | 383 void insnWithID(insn_t &Insn, unsigned Opcode) const { in insnWithID() argument
396 Insn.push_back(BIT_UNSET); in insnWithID()
398 Insn.push_back(bitFromBits(Bits, i)); in insnWithID()
412 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit,
440 const insn_t &Insn) const;
521 insn_t Insn; in Filter() local
524 Owner->insnWithID(Insn, Owner->Opcodes[i]); in Filter()
528 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits); in Filter()
955 bool FilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn, in fieldFromInsn() argument
960 if (Insn[StartBit + i] == BIT_UNSET) in fieldFromInsn()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/Disassembler/ |
| D | AVRDisassembler.cpp | 79 uint64_t &Size, uint32_t &Insn) { in readInstruction16() argument
86 Insn = (Bytes[0] << 0) | (Bytes[1] << 8); in readInstruction16()
92 uint64_t &Size, uint32_t &Insn) { in readInstruction32() argument
100 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24); in readInstruction32()
119 uint32_t Insn; in getInstruction() local
125 Result = readInstruction16(Bytes, Address, Size, Insn); in getInstruction()
131 Insn, Address, this, STI); in getInstruction()
139 Result = readInstruction32(Bytes, Address, Size, Insn); in getInstruction()
143 Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, in getInstruction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/Disassembler/ |
| D | BPFDisassembler.cpp | 129 static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn, in decodeMemoryOpValue() argument
131 unsigned Register = (Insn >> 16) & 0xf; in decodeMemoryOpValue()
133 unsigned Offset = (Insn & 0xffff); in decodeMemoryOpValue()
141 uint64_t &Size, uint64_t &Insn, in readInstruction64() argument
159 Insn = Make_64(Hi, Lo); in readInstruction64()
170 uint64_t Insn, Hi; in getInstruction() local
173 Result = readInstruction64(Bytes, Address, Size, Insn, IsLittleEndian); in getInstruction()
176 uint8_t InstClass = getInstClass(Insn); in getInstruction()
178 getInstSize(Insn) != BPF_DW && in getInstruction()
179 getInstMode(Insn) == BPF_MEM && in getInstruction()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/ |
| D | RuntimeDyldELFMips.cpp | 216 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); in applyMIPSRelocation() local
234 Insn = (Insn & 0xffff0000) | (Value & 0x0000ffff); in applyMIPSRelocation()
235 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
238 Insn = (Insn & 0xfffc0000) | (Value & 0x0003ffff); in applyMIPSRelocation()
239 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
242 Insn = (Insn & 0xfff80000) | (Value & 0x0007ffff); in applyMIPSRelocation()
243 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
246 Insn = (Insn & 0xffe00000) | (Value & 0x001fffff); in applyMIPSRelocation()
247 writeBytesUnaligned(Insn, TargetPtr, 4); in applyMIPSRelocation()
251 Insn = (Insn & 0xfc000000) | (Value & 0x03ffffff); in applyMIPSRelocation()
[all …]
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| D | RuntimeDyldMachOARM.h | 271 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); in resolveRelocation() local
274 Insn = (Insn & 0x8f00fbf0) | ((Value & 0xf000) >> 12) | in resolveRelocation()
278 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff); in resolveRelocation()
279 writeBytesUnaligned(Insn, LocalAddress, 4); in resolveRelocation()
|
| /external/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| D | RuntimeDyldELF.cpp | 509 uint32_t Insn = readBytesUnaligned(TargetPtr, 4); in resolveMIPSRelocation() local
519 Insn &= 0xfc000000; in resolveMIPSRelocation()
520 Insn |= (Value & 0x0fffffff) >> 2; in resolveMIPSRelocation()
521 writeBytesUnaligned(Insn, TargetPtr, 4); in resolveMIPSRelocation()
525 Insn &= 0xffff0000; in resolveMIPSRelocation()
526 Insn |= ((Value + 0x8000) >> 16) & 0xffff; in resolveMIPSRelocation()
527 writeBytesUnaligned(Insn, TargetPtr, 4); in resolveMIPSRelocation()
530 Insn &= 0xffff0000; in resolveMIPSRelocation()
531 Insn |= Value & 0xffff; in resolveMIPSRelocation()
532 writeBytesUnaligned(Insn, TargetPtr, 4); in resolveMIPSRelocation()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 255 uint32_t Insn; in getInstruction() local
260 Insn = support::endian::read32le(Bytes.data()); in getInstruction()
262 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); in getInstruction()
265 Insn = support::endian::read16le(Bytes.data()); in getInstruction()
271 Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Insn, Address, in getInstruction()
281 Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI); in getInstruction()
|
| /external/dexmaker/dexmaker/src/main/java/com/android/dx/ |
| D | Label.java | 20 import com.android.dx.rop.code.Insn;
32 final List<Insn> instructions = new ArrayList<>();
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsHazardSchedule.cpp | 97 I = std::find_if_not(I, E, [](const Iter &Insn) { return Insn->isTransient(); }); in getNextMachineInstr() argument
|
| /external/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/ |
| D | RuntimeDyldMachOARM.h | 163 uint32_t Insn = readBytesUnaligned(LocalAddress, 4); in resolveRelocation() local
164 Insn = (Insn & 0xfff0f000) | ((Value & 0xf000) << 4) | (Value & 0x0fff); in resolveRelocation()
165 writeBytesUnaligned(Insn, LocalAddress, 4); in resolveRelocation()
|