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Searched refs:IntVT (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DValueTypes.h296 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
297 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
298 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.h331 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
332 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
333 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp420 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
422 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
424 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
425 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
DTargetLowering.cpp3813 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), in expandFP_TO_SINT() local
3815 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT()
3816 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT()
3817 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
3819 IntVT); in expandFP_TO_SINT()
3820 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT); in expandFP_TO_SINT()
3821 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT()
3823 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); in expandFP_TO_SINT()
3827 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
3828 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT, DL))); in expandFP_TO_SINT()
[all …]
DFastISel.cpp424 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
425 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
433 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1701 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1702 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1705 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1711 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true, in selectFNeg()
1712 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1716 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
DLegalizeDAG.cpp1466 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1467 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1468 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN()
1477 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1478 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1492 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN()
1527 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
1528 SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT); in ExpandFABS()
1529 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue, in ExpandFABS()
DLegalizeFloatTypes.cpp941 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in SoftenFloatOp_FP_TO_XINT() local
942 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in SoftenFloatOp_FP_TO_XINT()
943 ++IntVT) { in SoftenFloatOp_FP_TO_XINT()
944 NVT = (MVT::SimpleValueType)IntVT; in SoftenFloatOp_FP_TO_XINT()
DDAGCombiner.cpp10030 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
10031 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
10032 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
11880 EVT IntVT = Int.getValueType(); in visitFNEG() local
11881 if (IntVT.isInteger() && !IntVT.isVector()) { in visitFNEG()
11887 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); in visitFNEG()
11890 SignMask = APInt::getSignMask(IntVT.getSizeInBits()); in visitFNEG()
11893 Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int, in visitFNEG()
11894 DAG.getConstant(SignMask, DL0, IntVT)); in visitFNEG()
11985 EVT IntVT = Int.getValueType(); in visitFABS() local
[all …]
DSelectionDAG.cpp5058 EVT IntVT = VT.getScalarType(); in getMemsetValue() local
5059 if (!IntVT.isInteger()) in getMemsetValue()
5060 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue()
5062 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
5067 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
5068 DAG.getConstant(Magic, dl, IntVT)); in getMemsetValue()
/external/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp430 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
432 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
434 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
435 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
DTargetLowering.cpp3097 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), in expandFP_TO_SINT() local
3099 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT()
3100 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT()
3101 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
3103 IntVT); in expandFP_TO_SINT()
3104 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT); in expandFP_TO_SINT()
3105 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT()
3107 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); in expandFP_TO_SINT()
3111 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
3112 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT, DL))); in expandFP_TO_SINT()
[all …]
DFastISel.cpp233 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
236 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
246 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1496 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1497 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1500 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1506 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true, in selectFNeg()
1507 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1511 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
DLegalizeDAG.cpp1442 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1443 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1444 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN()
1453 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1454 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1470 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1471 SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1473 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1474 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1507 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
[all …]
DDAGCombiner.cpp7680 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
7681 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
7682 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
9308 EVT IntVT = Int.getValueType(); in visitFNEG() local
9309 if (IntVT.isInteger() && !IntVT.isVector()) { in visitFNEG()
9315 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); in visitFNEG()
9318 SignMask = APInt::getSignBit(IntVT.getSizeInBits()); in visitFNEG()
9321 Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int, in visitFNEG()
9322 DAG.getConstant(SignMask, DL0, IntVT)); in visitFNEG()
9413 EVT IntVT = Int.getValueType(); in visitFABS() local
[all …]
DLegalizeFloatTypes.cpp898 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in SoftenFloatOp_FP_TO_XINT() local
899 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in SoftenFloatOp_FP_TO_XINT()
900 ++IntVT) { in SoftenFloatOp_FP_TO_XINT()
901 NVT = (MVT::SimpleValueType)IntVT; in SoftenFloatOp_FP_TO_XINT()
DSelectionDAG.cpp4088 EVT IntVT = VT.getScalarType(); in getMemsetValue() local
4089 if (!IntVT.isInteger()) in getMemsetValue()
4090 IntVT = EVT::getIntegerVT(*DAG.getContext(), IntVT.getSizeInBits()); in getMemsetValue()
4092 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value); in getMemsetValue()
4097 Value = DAG.getNode(ISD::MUL, dl, IntVT, Value, in getMemsetValue()
4098 DAG.getConstant(Magic, dl, IntVT)); in getMemsetValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1254 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter() local
1266 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract); in lowerKernargMemParameter()
4245 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT() local
4253 SDValue ExtVal = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Val); in lowerINSERT_VECTOR_ELT()
4261 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerINSERT_VECTOR_ELT()
4262 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT()
4263 DAG.getConstant(0xffff, SL, IntVT), in lowerINSERT_VECTOR_ELT()
4266 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
4267 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT, in lowerINSERT_VECTOR_ELT()
4268 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
[all …]
DAMDGPUISelLowering.cpp1452 MVT IntVT = MVT::i32; in LowerDIVREM24() local
1472 SDValue jq = DAG.getConstant(1, DL, IntVT); in LowerDIVREM24()
1514 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp4374 MVT IntVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits()); in lowerINSERT_VECTOR_ELT() local
4375 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT()
4378 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2); in lowerINSERT_VECTOR_ELT()
4401 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT() local
4402 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT()
4403 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp4663 MVT IntVT = MVT::getIntegerVT(VT.getScalarSizeInBits()); in lowerINSERT_VECTOR_ELT() local
4664 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements()); in lowerINSERT_VECTOR_ELT()
4667 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2); in lowerINSERT_VECTOR_ELT()
4690 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in lowerEXTRACT_VECTOR_ELT() local
4691 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements()); in lowerEXTRACT_VECTOR_ELT()
4692 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT, in lowerEXTRACT_VECTOR_ELT()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1237 MVT IntVT = MVT::i32; in LowerDIVREM24() local
1257 SDValue jq = DAG.getConstant(1, DL, IntVT); in LowerDIVREM24()
1296 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp2822 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32; in LowerFormalArguments() local
2823 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
27922 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32; in combineCompareEqual() local
27935 IntVT = MVT::i32; in combineCompareEqual()
27938 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF); in combineCompareEqual()
27939 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI, in combineCompareEqual()
27940 DAG.getConstant(1, DL, IntVT)); in combineCompareEqual()
29784 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements()); in lowerX86FPLogicOp() local
29786 SDValue Op0 = DAG.getBitcast(IntVT, N->getOperand(0)); in lowerX86FPLogicOp()
29787 SDValue Op1 = DAG.getBitcast(IntVT, N->getOperand(1)); in lowerX86FPLogicOp()
[all …]
DX86InstrAVX512.td102 ValueType IntVT = !cast<ValueType>(
7767 (_.IntVT _.RC:$src3),
7775 (_.IntVT (bitconvert (_.LdFrag addr:$src3))),
7784 (_.IntVT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7799 (_.IntVT _.RC:$src3),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp3291 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32; in LowerFormalArguments() local
3292 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
31506 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), Imm.getBitWidth()); in combinevXi1ConstantToInteger() local
31507 return DAG.getConstant(Imm, SDLoc(Op), IntVT); in combinevXi1ConstantToInteger()
34442 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32; in combineCompareEqual() local
34455 IntVT = MVT::i32; in combineCompareEqual()
34458 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF); in combineCompareEqual()
34459 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI, in combineCompareEqual()
34460 DAG.getConstant(1, DL, IntVT)); in combineCompareEqual()
37039 MVT IntVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64); in lowerX86FPLogicOp() local
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp7628 EVT IntVT = BV->getValueType(0); in performVectorCompareAndMaskUnaryOpCombine() local
7633 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); in performVectorCompareAndMaskUnaryOpCombine()
7634 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in performVectorCompareAndMaskUnaryOpCombine()

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