/external/llvm/lib/Target/AMDGPU/Disassembler/ |
D | AMDGPUDisassembler.cpp | 302 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) { in decodeFPImmed() argument 318 case 248: return MCOperand::createImm(Is32 ? // 1/(2*PI) in decodeFPImmed() 323 return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V)); in decodeFPImmed() 375 const bool Is32 = (Width == OPW32); in decodeSrcOp() local 381 return decodeFPImmed(Is32, Val); in decodeSrcOp() 386 return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val); in decodeSrcOp()
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D | AMDGPUDisassembler.h | 84 static MCOperand decodeFPImmed(bool Is32, unsigned Imm);
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/external/v8/src/builtins/ |
D | builtins-bigint-gen.cc | 33 if (!Is32()) { in TF_BUILTIN() 63 if (!Is32()) { in TF_BUILTIN()
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D | builtins-wasm-gen.cc | 57 if (!Is32()) { in TF_BUILTIN() 82 if (!Is32()) { in TF_BUILTIN()
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/external/v8/src/compiler/ |
D | machine-graph.cc | 31 return machine()->Is32() ? Int32Constant(static_cast<int32_t>(value)) in IntPtrConstant() 36 return machine()->Is32() ? Uint32Constant(static_cast<uint32_t>(value)) in UintPtrConstant()
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D | machine-operator.h | 930 bool Is32() const { return word() == MachineRepresentation::kWord32; } in NON_EXPORTED_BASE() 966 return Is32() ? Prefix##32##Suffix() : Prefix##64##Suffix(); \ in NON_EXPORTED_BASE() 973 return Is32() ? Word32Sar(kind) : Word64Sar(kind); in NON_EXPORTED_BASE()
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D | machine-graph-verifier.cc | 467 if (Is32()) { in Run() 713 static bool Is32() { in Is32() function in v8::internal::compiler::__anonf8ae49ab0111::MachineRepresentationChecker 813 if (Is32()) { in CheckValueInputIsTaggedOrPointer()
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D | wasm-compiler.cc | 870 } else if (m->Is32() && m->Word32Ctz().IsSupported()) { in Unop() 885 } else if (m->Is32() && m->Word32Popcnt().IsSupported()) { in Unop() 896 if (m->Is32()) { in Unop() 902 if (m->Is32()) { in Unop() 908 if (m->Is32()) { in Unop() 914 if (m->Is32()) { in Unop() 942 return mcgraph()->machine()->Is32() in Unop() 1482 DCHECK(mcgraph()->machine()->Is32()); in BuildF64CopySign() 2526 if (mcgraph()->machine()->Is32()) { in BuildI64DivS() 2552 if (mcgraph()->machine()->Is32()) { in BuildI64RemS() [all …]
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D | representation-change.cc | 1309 return (COMPRESS_POINTERS_BOOL || machine()->Is32()) in TaggedSignedOperatorFor() 1313 return (COMPRESS_POINTERS_BOOL || machine()->Is32()) in TaggedSignedOperatorFor() 1317 return (COMPRESS_POINTERS_BOOL || machine()->Is32()) in TaggedSignedOperatorFor()
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D | code-assembler.cc | 197 bool CodeAssembler::Is32() const { return raw_assembler()->machine()->Is32(); } in Is32() function in v8::internal::compiler::CodeAssembler
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D | int64-lowering.cc | 47 if (!machine()->Is32()) { in LowerGraph()
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D | raw-machine-assembler.h | 330 if (machine()->Is32()) { in WordNot()
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D | code-assembler.h | 388 bool Is32() const;
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D | effect-control-linearizer.cc | 4209 Node* index = machine()->Is32() ? code : __ ChangeUint32ToUint64(code); in LowerStringFromSingleCharCode() 4335 Node* index = machine()->Is32() ? code : __ ChangeUint32ToUint64(code); in LowerStringFromSingleCodePoint()
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/external/llvm/lib/Target/AMDGPU/ |
D | AMDGPUISelDAGToDAG.cpp | 1373 bool Is32 = (VT == MVT::i32); in SelectATOMIC_CMP_SWAP() local 1381 unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_ADDR64 : in SelectATOMIC_CMP_SWAP() 1398 unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET : in SelectATOMIC_CMP_SWAP() 1419 unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1; in SelectATOMIC_CMP_SWAP()
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/external/swiftshader/third_party/subzero/src/ |
D | IceTargetLoweringX8632Traits.h | 485 unsigned Is32 : 1; 513 (IntegerRegistersI32)[Entry.Val] = Entry.Is32;
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D | IceTargetLoweringX8664Traits.h | 515 unsigned Is32 : 1; 561 (IntegerRegistersI32)[Entry.Val] = Entry.Is32;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | AMDGPUISelDAGToDAG.cpp | 1777 bool Is32 = (VT == MVT::i32); in SelectATOMIC_CMP_SWAP() local 1785 unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN : in SelectATOMIC_CMP_SWAP() 1802 unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN : in SelectATOMIC_CMP_SWAP() 1823 unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1; in SelectATOMIC_CMP_SWAP()
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfo.td | 4116 class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32, 4123 let Inst{26} = Is32;
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