| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 93 unsigned IsDef : 1; variable
361 return !IsDef; in isUse()
366 return IsDef; in isDef()
376 return IsDeadOrKill & IsDef; in isDead()
381 return IsDeadOrKill & !IsDef; in isKill()
490 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
496 assert(isReg() && IsDef && "Wrong MachineOperand mutator");
513 assert(isReg() && IsDef && "Wrong MachineOperand mutator");
518 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
766 Op.IsDef = isDef;
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 87 bool IsDef : 1; variable
279 return !IsDef; in isUse()
284 return IsDef; in isDef()
376 assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
382 assert(isReg() && IsDef && "Wrong MachineOperand accessor");
397 assert(isReg() && IsDef && "Wrong MachineOperand accessor");
402 assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
616 Op.IsDef = isDef;
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| D | MCInstrDescView.cpp | 28 Operand.IsDef = (OpIndex < MCInstrDesc.getNumDefs()); in Instruction()
42 Operand.IsDef = true; in Instruction()
52 Operand.IsDef = false; in Instruction()
80 auto &Registers = Op.IsDef ? DefRegisters : UseRegisters; in Instruction()
167 if (Op.Tracker && Op.IsDef == SelectDef) { in addOperandIfAlias()
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| D | Uops.cpp | 109 if (Op.IsDef) in hasTiedOperands()
172 if (Op.Tracker && Op.IsExplicit && Op.IsDef) { in generatePrototype()
184 if (Op.Tracker && Op.IsExplicit && !Op.IsDef) { in generatePrototype()
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| D | BenchmarkRunner.cpp | 164 if (!Op.IsDef) { in computeRegsToDef()
174 if (Op.IsDef) { in computeRegsToDef()
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| D | MCInstrDescView.h | 60 bool IsDef = false; member
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| D | Assembler.cpp | 97 const bool IsDef = OpIndex < MCID.getNumDefs(); in fillMachineFunction() local
100 if (IsDef && !OpInfo.isOptionalDef()) in fillMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | InstrDocsEmitter.cpp | 154 bool IsDef = i < II->Operands.NumDefs; in EmitInstrDocs() local
168 OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName() in EmitInstrDocs()
179 OS << "* " << (IsDef ? "DEF" : "USE") << " ``" << Op.Rec->getName() in EmitInstrDocs()
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| /external/llvm/lib/Target/Hexagon/ |
| D | RDFDeadCode.cpp | 125 if (DFG.IsDef(RA)) in collect()
140 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) in collect()
215 else if (DFG.IsDef(RA)) in erase()
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| D | HexagonRDFOpt.cpp | 152 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
244 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) { in rewrite()
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| D | HexagonFrameLowering.h | 142 bool IsDef, bool IsKill) const;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | RDFDeadCode.cpp | 136 if (DFG.IsDef(RA)) in collect()
151 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) in collect()
226 else if (DFG.IsDef(RA)) in erase()
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| D | HexagonConstExtenders.cpp | 328 bool IsDef = false; member
502 if (ED.IsDef) in operator <<()
1170 ED.IsDef = true; in recordExtender()
1190 ED.IsDef = true; in recordExtender()
1195 ED.IsDef = true; in recordExtender()
1199 ED.IsDef = true; in recordExtender()
1271 if (!ED.IsDef) in assignInits()
1291 if (ED.IsDef) in assignInits()
1820 assert((!ED.IsDef || ED.Rd.Reg != 0) && "Missing Rd for def"); in replaceInstr()
1845 if (ED.IsDef && Diff != 0) { in replaceInstr()
[all …]
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| D | HexagonRDFOpt.cpp | 168 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
258 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) { in rewrite()
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| D | HexagonFrameLowering.h | 168 bool IsDef, bool IsKill) const;
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| D | RDFCopy.cpp | 145 for (NodeAddr<DefNode*> DA : SA.Addr->members_if(DFG.IsDef, DFG)) { in run()
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| D | HexagonOptAddrMode.cpp | 183 if ((DFG->IsDef(AA) && AA.Id != OffsetRegRD) || in canRemoveAddasl()
246 for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) { in getAllRealUses()
307 if ((DFG->IsDef(AA) && AA.Id != LRExtRegRD) || in isSafeToExtLR()
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | split-index-tc.ll | 23 …%IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %0…
24 %1 = bitcast [3 x i8]* %IsDef.i to i24*
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | split-index-tc.ll | 23 …%IsDef.i = getelementptr inbounds %"class.llvm::MachineOperand", %"class.llvm::MachineOperand"* %0…
24 %1 = bitcast [3 x i8]* %IsDef.i to i24*
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| /external/llvm/lib/CodeGen/ |
| D | MIRPrinter.cpp | 124 const MachineRegisterInfo *MRI = nullptr, bool IsDef = false);
752 const MachineRegisterInfo *MRI, bool IsDef) { in print() argument
758 else if (!IsDef && Op.isDef()) in print()
779 assert((!IsDef || MRI) && "for IsDef, MRI must be provided"); in print()
780 if (IsDef && MRI->getSize(Op.getReg())) in print()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.h | 33 void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
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| D | MipsDelaySlotFiller.cpp | 132 bool IsDef) const;
432 unsigned Reg, bool IsDef) const { in checkRegDefsUses()
433 if (IsDef) { in checkRegDefsUses()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.h | 31 void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
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| D | MipsDelaySlotFiller.cpp | 112 bool IsDef) const;
404 unsigned Reg, bool IsDef) const { in checkRegDefsUses()
405 if (IsDef) { in checkRegDefsUses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineOperand.cpp | 100 if (IsDef == Val) in setIsDef()
107 IsDef = Val; in setIsDef()
111 IsDef = Val; in setIsDef()
237 IsDef = isDef; in ChangeToRegister()
|