| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsAsmBackend.h | 31 bool IsLittle; // Big or little endian variable
35 MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle, in MipsAsmBackend() argument
37 : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {} in MipsAsmBackend()
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| D | MipsAsmBackend.cpp | 209 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); in createObjectWriter()
270 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) in applyFixup()
282 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) in applyFixup()
442 if (IsLittle) in getFixupKindInfo()
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| D | MipsMCCodeEmitter.h | 44 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) in MipsMCCodeEmitter() argument
45 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} in MipsMCCodeEmitter()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAsmBackendELF.h | 22 bool IsLittle) in ARMAsmBackendELF() argument
23 : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {} in ARMAsmBackendELF()
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| D | ARMAsmBackend.h | 26 ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle) in ARMAsmBackend() argument
29 IsLittleEndian(IsLittle) {} in ARMAsmBackend()
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| D | ARMMCCodeEmitter.cpp | 47 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) in ARMMCCodeEmitter() argument
48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { in ARMMCCodeEmitter()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.cpp | 90 const ARMBaseTargetMachine &TM, bool IsLittle) in ARMSubtarget() argument
92 CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), in ARMSubtarget()
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| D | ARMSubtarget.h | 326 bool IsLittle; variable
347 const ARMBaseTargetMachine &TM, bool IsLittle);
579 bool isLittle() const { return IsLittle; } in isLittle()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.cpp | 96 const ARMBaseTargetMachine &TM, bool IsLittle) in ARMSubtarget() argument
98 CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), in ARMSubtarget()
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| D | ARMSubtarget.h | 436 bool IsLittle; variable
457 const ARMBaseTargetMachine &TM, bool IsLittle);
733 bool isLittle() const { return IsLittle; } in isLittle()
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| D | ARMCallLowering.cpp | 159 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); in assignCustomValue() local
160 if (!IsLittle) in assignCustomValue()
390 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); in assignCustomValue() local
391 if (!IsLittle) in assignCustomValue()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64Subtarget.h | 98 bool IsLittle; variable
214 bool isLittleEndian() const { return IsLittle; } in isLittleEndian()
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| D | AArch64Subtarget.cpp | 92 ReserveX18(TT.isOSDarwin() || TT.isAndroid()), IsLittle(LittleEndian), in AArch64Subtarget()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSubtarget.h | 55 bool IsLittle; variable
220 bool isLittle() const { return IsLittle; } in isLittle()
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| D | MipsSubtarget.cpp | 66 IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), in MipsSubtarget()
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| D | MipsISelLowering.cpp | 2275 bool IsLittle = Subtarget.isLittle(); in lowerLOAD() local
2289 IsLittle ? 7 : 0); in lowerLOAD()
2291 IsLittle ? 0 : 7); in lowerLOAD()
2295 IsLittle ? 3 : 0); in lowerLOAD()
2297 IsLittle ? 0 : 3); in lowerLOAD()
2345 bool IsLittle) { in lowerUnalignedIntStore() argument
2357 IsLittle ? 3 : 0); in lowerUnalignedIntStore()
2358 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore()
2368 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); in lowerUnalignedIntStore()
2369 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); in lowerUnalignedIntStore()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSubtarget.h | 74 bool IsLittle; variable
269 bool isLittle() const { return IsLittle; } in isLittle()
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| D | MipsSubtarget.cpp | 75 IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), in MipsSubtarget()
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| D | MipsISelLowering.cpp | 2468 bool IsLittle = Subtarget.isLittle(); in lowerLOAD() local
2482 IsLittle ? 7 : 0); in lowerLOAD()
2484 IsLittle ? 0 : 7); in lowerLOAD()
2488 IsLittle ? 3 : 0); in lowerLOAD()
2490 IsLittle ? 0 : 3); in lowerLOAD()
2538 bool IsLittle) { in lowerUnalignedIntStore() argument
2550 IsLittle ? 3 : 0); in lowerUnalignedIntStore()
2551 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore()
2561 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); in lowerUnalignedIntStore()
2562 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); in lowerUnalignedIntStore()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64Subtarget.h | 146 bool IsLittle; variable
300 bool isLittleEndian() const { return IsLittle; } in isLittleEndian()
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| D | AArch64Subtarget.cpp | 155 ReserveX18(AArch64::isX18ReservedByDefault(TT)), IsLittle(LittleEndian), in AArch64Subtarget()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.h | 40 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) in MipsMCCodeEmitter() argument
41 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} in MipsMCCodeEmitter()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 57 ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle) in ARMMCCodeEmitter() argument
58 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) { in ARMMCCodeEmitter()
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