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Searched refs:IsSignallingNaN (Results 1 – 9 of 9) sorted by relevance

/external/v8/src/codegen/arm64/
Dutils-arm64.h72 inline bool IsSignallingNaN(double num) { in IsSignallingNaN() function
80 inline bool IsSignallingNaN(float num) { in IsSignallingNaN() function
88 inline bool IsSignallingNaN(float16 num) { in IsSignallingNaN() function
95 return std::isnan(num) && !IsSignallingNaN(num); in IsQuietNaN()
/external/vixl/src/
Dutils-vixl.cc300 if (IsSignallingNaN(value)) { in FPToFloat()
345 if (IsSignallingNaN(value)) { in FPToFloat()
408 if (IsSignallingNaN(value)) { in FPToDouble()
462 if (IsSignallingNaN(value)) { in FPToFloat16()
517 if (IsSignallingNaN(value)) { in FPToFloat16()
Dutils-vixl.h390 inline bool IsSignallingNaN(double num) { in IsSignallingNaN() function
400 inline bool IsSignallingNaN(float num) { in IsSignallingNaN() function
410 inline bool IsSignallingNaN(Float16 num) { in IsSignallingNaN() function
418 return IsNaN(num) && !IsSignallingNaN(num); in IsQuietNaN()
/external/vixl/test/aarch64/
Dtest-assembler-fp-aarch64.cc914 VIXL_ASSERT(IsSignallingNaN(s1)); in TEST()
915 VIXL_ASSERT(IsSignallingNaN(s2)); in TEST()
916 VIXL_ASSERT(IsSignallingNaN(sa)); in TEST()
1012 VIXL_ASSERT(IsSignallingNaN(s1)); in TEST()
1013 VIXL_ASSERT(IsSignallingNaN(s2)); in TEST()
1014 VIXL_ASSERT(IsSignallingNaN(sa)); in TEST()
1307 VIXL_ASSERT(IsSignallingNaN(snan)); in TEST()
1411 VIXL_ASSERT(IsSignallingNaN(snan)); in TEST()
4687 VIXL_ASSERT(IsSignallingNaN(sn)); in TEST()
4763 VIXL_ASSERT(IsSignallingNaN(sn)); in TEST()
[all …]
Dtest-assembler-neon-aarch64.cc10568 if (IsSignallingNaN(n)) { in MinMaxHelper()
10571 } else if (IsSignallingNaN(m)) { in MinMaxHelper()
10612 VIXL_ASSERT(IsSignallingNaN(snan)); in TEST()
/external/vixl/src/aarch64/
Dsimulator-aarch64.h3311 if (IsSignallingNaN(op)) {
3319 if (IsSignallingNaN(op1)) {
3321 } else if (IsSignallingNaN(op2)) {
3336 if (IsSignallingNaN(op1)) {
3338 } else if (IsSignallingNaN(op2)) {
3340 } else if (IsSignallingNaN(op3)) {
Dsimulator-aarch64.cc139 VIXL_ASSERT(IsSignallingNaN(RawbitsToDouble(nan_bits[0] & kDRegMask))); in ResetState()
140 VIXL_ASSERT(IsSignallingNaN(RawbitsToFloat(nan_bits[0] & kSRegMask))); in ResetState()
477 if (IsSignallingNaN(val0) || IsSignallingNaN(val1) || in FPCompare()
/external/v8/src/execution/arm64/
Dsimulator-arm64.h2458 if (IsSignallingNaN(op1)) { in FPProcessNaNs()
2460 } else if (IsSignallingNaN(op2)) { in FPProcessNaNs()
2475 if (IsSignallingNaN(op1)) { in FPProcessNaNs3()
2477 } else if (IsSignallingNaN(op2)) { in FPProcessNaNs3()
2479 } else if (IsSignallingNaN(op3)) { in FPProcessNaNs3()
Dsimulator-logic-arm64.cc94 if (IsSignallingNaN(value)) { in FPToDouble()
163 if (IsSignallingNaN(value)) { in FPToFloat()
208 if (IsSignallingNaN(value)) { in FPToFloat16()
256 if (IsSignallingNaN(value)) { in FPToFloat16()
299 if (IsSignallingNaN(value)) { in FPToFloat()