| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 118 bool IsUndef : 1; variable
304 return IsUndef; in isUndef()
388 IsUndef = Val;
620 Op.IsUndef = isUndef;
|
| D | MachineInstr.h | 1101 void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 128 unsigned IsUndef : 1; variable
386 return IsUndef; in isUndef()
502 IsUndef = Val;
770 Op.IsUndef = isUndef;
|
| D | MachineInstr.h | 1189 void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
|
| /external/llvm/test/CodeGen/X86/ |
| D | pr23103.ll | 3 ; When commuting a VADDSDrr instruction, verify that the 'IsUndef' flag is
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | pr23103.ll | 4 ; When commuting a VADDSDrr instruction, verify that the 'IsUndef' flag is
|
| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 199 IsUndef = isUndef; in ChangeToRegister()
2079 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) { in setRegisterDefReadUndef() argument
2083 MO.setIsUndef(IsUndef); in setRegisterDefReadUndef()
|
| D | RegisterCoalescer.cpp | 1221 bool IsUndef = true; in addUndefFlag() local
1226 IsUndef = false; in addUndefFlag()
1230 if (IsUndef) { in addUndefFlag()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 368 bool IsSplat = true, IsUndef = true; in buildHvxVectorReg() local
373 IsUndef = false; in buildHvxVectorReg()
379 if (IsUndef) in buildHvxVectorReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1700 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) { in setRegisterDefReadUndef() argument
1704 MO.setIsUndef(IsUndef); in setRegisterDefReadUndef()
|
| D | RegisterCoalescer.cpp | 1504 bool IsUndef = true; in addUndefFlag() local
1509 IsUndef = false; in addUndefFlag()
1513 if (IsUndef) { in addUndefFlag()
|
| D | MachineOperand.cpp | 241 IsUndef = isUndef; in ChangeToRegister()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1250 bool IsUndef = MI.getOperand(1).isUndef(); in expandPostRAPseudo() local
1260 RegState::Implicit | (IsUndef ? RegState::Undef : 0)); in expandPostRAPseudo()
1354 bool IsUndef = RegOp.isUndef(); in swapRegAndNonRegOperand() local
1364 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug); in swapRegAndNonRegOperand()
|
| /external/clang/lib/Serialization/ |
| D | ASTReader.cpp | 465 bool IsUndef = PPOpts.Macros[I].second; in collectMacroDefinitions() local
472 if (IsUndef) { in collectMacroDefinitions()
4822 bool IsUndef = Record[Idx++]; in ParsePreprocessorOptions() local
4823 PPOpts.Macros.push_back(std::make_pair(Macro, IsUndef)); in ParsePreprocessorOptions()
|
| /external/llvm/bindings/go/llvm/ |
| D | ir.go | 739 func (v Value) IsUndef() bool { return C.LLVMIsUndef(v.C) != 0 } func
|
| /external/swiftshader/third_party/llvm-7.0/llvm/bindings/go/llvm/ |
| D | ir.go | 772 func (v Value) IsUndef() bool { return C.LLVMIsUndef(v.C) != 0 } func
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4376 bool IsUndef = Values[i] < 0 && IsMask; in getConstVector() local
4377 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) : in getConstVector()
4381 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) : in getConstVector()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5020 bool IsUndef = Values[i] < 0 && IsMask; in getConstVector() local
5021 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) : in getConstVector()
5025 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) : in getConstVector()
|