| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | licm-tocReg.ll | 21 ; %7 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
24 ; %10 = LWZ 0, killed %9 :: (volatile dereferenceable load 4 from @gb)
25 ; %0 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
53 ; %15 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
56 ; %18 = LWZ 0, killed %17 :: (volatile dereferenceable load 4 from @gb)
57 ; %3 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
|
| D | no-rlwimi-trivial-commute.mir | 75 %2 = LWZ 0, %1 :: (load 4 from %ir.0)
|
| D | convert-rr-to-ri-instrs.mir | 2633 ; CHECK: LWZ 1000, killed %6
2640 ; CHECK: LWZ 1000, killed %11
3110 %7 = LWZ 0, %stack.4 :: (load 4 from %stack.4)
3115 %12 = LWZ 0, %stack.1 :: (load 4 from %stack.1)
3120 %17 = LWZ 0, %stack.2 :: (load 4 from %stack.2)
3125 %22 = LWZ 0, %stack.3 :: (load 4 from %stack.3)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/PowerPC/ |
| D | unordered-implicit-registers.mir | 37 %1 = LWZ 0, %0 :: (load 4 from %ir.p)
|
| /external/llvm/test/CodeGen/MIR/PowerPC/ |
| D | unordered-implicit-registers.mir | 38 %1 = LWZ 0, %0 :: (load 4 from %ir.p)
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
394 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
554 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRRestore()
641 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRBitRestore()
714 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), in lowerVRSAVERestore()
|
| D | PPCAsmPrinter.cpp | 542 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
572 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
777 TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ); in EmitInstruction()
807 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LWZ) in EmitInstruction()
|
| D | PPCInstrInfo.cpp | 269 case PPC::LWZ: in isLoadFromStackSlot()
1101 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), in LoadRegFromStackSlot()
1869 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()
|
| D | PPCFrameLowering.cpp | 1137 : PPC::LWZ ); in emitEpilogue()
1794 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), in restoreCRs()
|
| D | PPCFastISel.cpp | 498 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) : in PPCEmitLoad()
574 case PPC::LWZ: Opc = PPC::LWZX; break; in PPCEmitLoad()
|
| D | PPCISelLowering.cpp | 8827 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP) in emitEHSjLjLongJmp()
8839 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp) in emitEHSjLjLongJmp()
8851 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP) in emitEHSjLjLongJmp()
8863 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP) in emitEHSjLjLongJmp()
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | no-rlwimi-trivial-commute.mir | 78 %2 = LWZ 0, %1 :: (load 4 from %ir.0)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 82 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
473 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
635 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRRestore()
722 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRBitRestore()
795 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), in lowerVRSAVERestore()
|
| D | PPCAsmPrinter.cpp | 625 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
656 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
866 TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ); in EmitInstruction()
896 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LWZ) in EmitInstruction()
|
| D | PPCInstrInfo.cpp | 2107 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()
2360 {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, in getLoadOpcodesForSpillArray()
2365 {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, in getLoadOpcodesForSpillArray()
2822 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break; in instrHasImmForm()
3203 Opcode == PPC::LWZ || Opcode == PPC::LWZX || in isZeroExtendingOp()
|
| D | PPCFrameLowering.cpp | 1265 : PPC::LWZ ); in emitEpilogue()
2042 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), in restoreCRs()
|
| D | PPCFastISel.cpp | 500 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
576 case PPC::LWZ: Opc = PPC::LWZX; break; in PPCEmitLoad()
|
| D | PPCMIPeephole.cpp | 577 if (SrcMI->getOpcode() == PPC::LWZ || in simplifyCode()
|
| D | P9InstrResources.td | 747 (instregex "LWZ(8|CIX|X|X8|XTLS|XTLS_32)?(_)?$"),
|
| /external/v8/src/codegen/ppc/ |
| D | assembler-ppc-inl.h | 309 const uint32_t kLoadIntptrOpcode = LWZ;
|
| D | constants-ppc.h | 1793 V(lwz, LWZ, 0x80000000) \
|
| D | assembler-ppc.cc | 977 d_form(LWZ, dst, src.ra(), src.offset(), true); in lwz()
|
| /external/v8/src/diagnostics/ppc/ |
| D | disasm-ppc.cc | 1449 case LWZ: { in InstructionDecode()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_common.c | 185 #define LWZ (HI(32)) macro
602 #define STACK_LOAD LWZ
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenMCCodeEmitter.inc | 1022 UINT64_C(2147483648), // LWZ
2523 case PPC::LWZ:
6611 0, // LWZ = 1009
|